| Message ID | 20230227112030.5229-1-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Implement UHBR bandwidth check | expand |
On Mon, Feb 27, 2023 at 01:20:30PM +0200, Stanislav Lisovskiy wrote: > According to spec, we should check if output_bpp * pixel_rate is less > than DDI clock * 72, if UHBR is used. > > v2: - s/pipe_config/crtc_state/ (Jani Nikula) > - Merged previous patch into that one, to remove empty function(Jani Nikula) > > HSDES: 1406899791 > BSPEC: 49259 > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 28 +++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index a860cbc5dbea..d0e2e37cd758 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -45,6 +45,26 @@ > #include "intel_hotplug.h" > #include "skl_scaler.h" > > +static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp, > + const struct drm_display_mode *adjusted_mode, > + struct intel_crtc_state *crtc_state) > +{ > + if (intel_dp_is_uhbr(crtc_state)) { > + int output_bpp = bpp; > + /* DisplayPort 2 128b/132b, bits per lane is always 32 */ > + int symbol_clock = crtc_state->port_clock / 32; > + > + if (output_bpp * adjusted_mode->crtc_clock >= > + symbol_clock * 72) { > + drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", > + output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72); > + return -EINVAL; > + } You're still doing this for non-DSC as well. Did we get any clarification whether that is correct or not? > + } > + > + return 0; > +} > + > static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, > struct intel_crtc_state *crtc_state, > int max_bpp, > @@ -87,6 +107,10 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, > > drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); > > + ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state); > + if (ret) > + continue; > + > slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, > connector->port, > crtc_state->pbn); > @@ -104,8 +128,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, > } > } > > - /* Despite slots are non-zero, we still failed the atomic check */ > - if (ret && slots >= 0) > + /* We failed to find a proper bpp/timeslots, return error */ > + if (ret) > slots = ret; > > if (slots < 0) { > -- > 2.37.3
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a860cbc5dbea..d0e2e37cd758 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -45,6 +45,26 @@ #include "intel_hotplug.h" #include "skl_scaler.h" +static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp, + const struct drm_display_mode *adjusted_mode, + struct intel_crtc_state *crtc_state) +{ + if (intel_dp_is_uhbr(crtc_state)) { + int output_bpp = bpp; + /* DisplayPort 2 128b/132b, bits per lane is always 32 */ + int symbol_clock = crtc_state->port_clock / 32; + + if (output_bpp * adjusted_mode->crtc_clock >= + symbol_clock * 72) { + drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", + output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72); + return -EINVAL; + } + } + + return 0; +} + static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, int max_bpp, @@ -87,6 +107,10 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); + ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state); + if (ret) + continue; + slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, connector->port, crtc_state->pbn); @@ -104,8 +128,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, } } - /* Despite slots are non-zero, we still failed the atomic check */ - if (ret && slots >= 0) + /* We failed to find a proper bpp/timeslots, return error */ + if (ret) slots = ret; if (slots < 0) {
According to spec, we should check if output_bpp * pixel_rate is less than DDI clock * 72, if UHBR is used. v2: - s/pipe_config/crtc_state/ (Jani Nikula) - Merged previous patch into that one, to remove empty function(Jani Nikula) HSDES: 1406899791 BSPEC: 49259 Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 28 +++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-)