From patchwork Tue Mar 7 13:49:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13163591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A424EC6FD1A for ; Tue, 7 Mar 2023 13:49:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 85F4410E4CC; Tue, 7 Mar 2023 13:49:16 +0000 (UTC) Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0634610E4B2 for ; Tue, 7 Mar 2023 13:49:11 +0000 (UTC) Received: by mail-lj1-x232.google.com with SMTP id t14so13196944ljd.5 for ; Tue, 07 Mar 2023 05:49:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678196949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C00WLLY6BRHuPhABrtxiqlYfBItYgfyJkU1QDvQQHNw=; b=VHzD5vFnu+2CSJV5nEv//ilP2CdFYhxruRgksVjxiHK4kwk+a45GY96Cis9LfF+GKB Fl0tqfb27xICa4MjqL0S9rHS12x9e+LTXzEiAXaSMU3waaHQKSv9IcCR5/VZepgdmpKE vp/02ugMrHJXwqMeJ1cfT743PVHIGcS0eMC3yQ4/8+c1aHb3tCxf71bFeRw0XrRp1QFB ra7huasdY547XWi9CrTeg7GDnhR/LuYSq65FXAHHMiffmp3qIs+rGMhwLrdn0nquyb6Y j+oLMmTjcW0cZRv+bLKKXUyScpkNPHhANsMERMNnxFf+5ynE5KFhjimpu5ItdL02UnMP FUzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678196949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C00WLLY6BRHuPhABrtxiqlYfBItYgfyJkU1QDvQQHNw=; b=qv3XlSveDF/mImPBxtue8gi8FupHu4MRgLJZlFevyIkyrLm7qx937RdJWO8elXfJtw m+Gq+TdGetrFMPnUVeuShBueuP88plWrNr1aDhG8vMJTcMG8L+C6I0g3RyOeI4MBFiBZ MrSD3s9nfRlsqGGqdD7fOWHk7IueR13I2BqNEzB40+8w4iNVCaf7dMfnjzCufpMlol1e /L/+86cjM0uT2F7yTMTj9zIEww2eWCMby+hPgyZUBchvQvmtZNgRMEJ4OdruvdV0T65b 1FDcOSxUF2qxsjXwabhAhabvAjvmwnvW6w8krF5GTqWLthOL22GKBvqCnYe1cNc1VVDK uImw== X-Gm-Message-State: AO0yUKV4kSQ9+b6amnt24LDlOqZoYt1Gqzu4rKhC7raMztwQuVc4kUkh XzkWpV2cunIt0f6oGPpwfn/mpg== X-Google-Smtp-Source: AK7set++M3LP4rz1Yp/02PuUkSXvXgd0Jc1fytshpLpA1bLmvxjDnEsaMcBCABEBruvrkj6FgfXhfg== X-Received: by 2002:a2e:910d:0:b0:295:c39c:d8ab with SMTP id m13-20020a2e910d000000b00295c39cd8abmr4015759ljg.39.1678196949419; Tue, 07 Mar 2023 05:49:09 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id u14-20020a2e91ce000000b0029597ebacd0sm2128991ljg.64.2023.03.07.05.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:49:09 -0800 (PST) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Date: Tue, 7 Mar 2023 15:49:00 +0200 Message-Id: <20230307134901.322560-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230307134901.322560-1-dmitry.baryshkov@linaro.org> References: <20230307134901.322560-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 09/10] drm/display/dsc: add helper to set semi-const parameters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, intel-gfx@lists.freedesktop.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a helper setting config values which are typically constant across operating modes (table E-4 of the standard) and mux_word_size (which is a const according to 3.5.2). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/display/drm_dsc_helper.c | 21 +++++++++++++++++++++ include/drm/display/drm_dsc_helper.h | 1 + 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index 65e810a54257..10ba413d8bf1 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -270,6 +270,27 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, } EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +/** + * drm_dsc_set_const_params() - Set DSC parameters considered typically + * constant across operation modes + * + * @vdsc_cfg: + * DSC Configuration data partially filled by driver + */ +void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg) +{ + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; + vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; + vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST; + vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST; + + if (vdsc_cfg->bits_per_component <= 10) + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; + else + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; +} +EXPORT_SYMBOL(drm_dsc_set_const_params); + /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ static const u16 drm_dsc_rc_buf_thresh[] = { 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 0bb0c3afd740..4448c482b092 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); +void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg); void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);