From patchwork Wed Mar 8 15:53:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13166067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2788DC678D5 for ; Wed, 8 Mar 2023 15:54:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 18A8B10E683; Wed, 8 Mar 2023 15:54:07 +0000 (UTC) Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8DA7E10E646; Wed, 8 Mar 2023 15:53:56 +0000 (UTC) Received: by mail-pf1-x435.google.com with SMTP id y10so10519613pfi.8; Wed, 08 Mar 2023 07:53:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678290836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YdpWGjES0Y3k3qZ7i2dzOojVVvIPqxdmlaSdfT3piAE=; b=bPsykuRekJqvfgn0QphkXZW1kbOC2zL+9xvl5K1J0hPbszzO0yc2plNdnxjifY6/Kn 8kUDyXlvkjolExMm7MNqhvI1LqddINmHW9/2wvWogVuY/idOhg9WrqMt88UVfCY/r/gF ms9lu7V9w+IaOaoC19uWO8s2PJnwRu4wXb86hP18wyj8iUZT1LzPvADYm2kBtvnz9Cov 6UfOMnB52gA6MndIhCiFF+SX1oWfXsIZhsZME9S0RSHW3hB72gn3HrWYNzteoxJA0+yz 8ewaOc0d/XIumHSWkMLZFwe7+RYHALUcHLNa8yIQWqF+q55eVydyD1xckvbrMZanwNJU iiYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678290836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YdpWGjES0Y3k3qZ7i2dzOojVVvIPqxdmlaSdfT3piAE=; b=kuWG2TMJCqpI/ysiT8xHINYl0JQOl0Q/rW3Rlc36S1hYxtRtRhKYLZbeKOY4zQHBib WeHNoyG1lf7CEyySN1yD86EzR4kcwMgxE2GPum/2BgLuM9IhytqOKKYJr2IQ6yFl1h2U T97Di+iiWVs6SA/miW7olz2LKualT13TCFdR9c9PMzlDWVpRn7gePvx1pIgm7sgNfKHV uhe4Rk1G7YA0RzOcIrKGAZknOGqMcdD39ObDmQhg6liAbsLwDeD1hbOaws5+8XT0cQox xSUNJXa+B/s2aH+5c/0BokTLyQt4f3pFRYUdJdf7cxXwkQ/u1zQ546KlCFPs8O/LkvWp Zisw== X-Gm-Message-State: AO0yUKVObQvnS6JOmhD/ICx0DkO6kFvNVzKW2v5IvrUTplos6GuOeUxD AX7+SOw7suFvES71tdUA+vrJB1IrrXY= X-Google-Smtp-Source: AK7set/golHYQrcgsxdjgbRRvUAr3kWxuVqTtG/RHJrceMV4N+LNFOTKe2AsJ/U+/1faG3XFRkogdA== X-Received: by 2002:a62:6583:0:b0:5cd:81a7:4094 with SMTP id z125-20020a626583000000b005cd81a74094mr15501800pfb.5.1678290835774; Wed, 08 Mar 2023 07:53:55 -0800 (PST) Received: from localhost ([2a00:79e1:abd:4a00:61b:48ed:72ab:435b]) by smtp.gmail.com with ESMTPSA id s1-20020aa78281000000b0059435689e36sm9823399pfm.170.2023.03.08.07.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 07:53:55 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Date: Wed, 8 Mar 2023 07:53:04 -0800 Message-Id: <20230308155322.344664-14-robdclark@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308155322.344664-1-robdclark@gmail.com> References: <20230308155322.344664-1-robdclark@gmail.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 13/15] drm/msm: Add wait-boost support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Daniel Vetter , =?utf-8?q?Christian_K=C3=B6nig?= , intel-gfx@lists.freedesktop.org, Bas Nieuwenhuizen , Abhinav Kumar , open list , Luben Tuikov , David Airlie , Rodrigo Vivi , Dmitry Baryshkov , Matt Turner , freedreno@lists.freedesktop.org, "open list:DRM DRIVER FOR MSM ADRENO GPU" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Rob Clark Add a way for various userspace waits to signal urgency. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_drv.c | 12 ++++++++---- drivers/gpu/drm/msm/msm_gem.c | 5 +++++ include/uapi/drm/msm_drm.h | 14 ++++++++++++-- 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index aca48c868c14..f6764a86b2da 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -46,6 +46,7 @@ * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT + * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST) */ #define MSM_VERSION_MAJOR 1 #define MSM_VERSION_MINOR 10 @@ -899,7 +900,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data, } static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, - ktime_t timeout) + ktime_t timeout, uint32_t flags) { struct dma_fence *fence; int ret; @@ -929,6 +930,9 @@ static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, if (!fence) return 0; + if (flags & MSM_WAIT_FENCE_BOOST) + dma_fence_set_deadline(fence, ktime_get()); + ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); if (ret == 0) { ret = -ETIMEDOUT; @@ -949,8 +953,8 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, struct msm_gpu_submitqueue *queue; int ret; - if (args->pad) { - DRM_ERROR("invalid pad: %08x\n", args->pad); + if (args->flags & ~MSM_WAIT_FENCE_FLAGS) { + DRM_ERROR("invalid flags: %08x\n", args->flags); return -EINVAL; } @@ -961,7 +965,7 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, if (!queue) return -ENOENT; - ret = wait_fence(queue, args->fence, to_ktime(args->timeout)); + ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags); msm_submitqueue_put(queue); diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 1dee0d18abbb..dd4a0d773f6e 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -846,6 +846,11 @@ int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout) op & MSM_PREP_NOSYNC ? 0 : timeout_to_jiffies(timeout); long ret; + if (op & MSM_PREP_BOOST) { + dma_resv_set_deadline(obj->resv, dma_resv_usage_rw(write), + ktime_get()); + } + ret = dma_resv_wait_timeout(obj->resv, dma_resv_usage_rw(write), true, remain); if (ret == 0) diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 329100016e7c..dbf0d6f43fa9 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -151,8 +151,13 @@ struct drm_msm_gem_info { #define MSM_PREP_READ 0x01 #define MSM_PREP_WRITE 0x02 #define MSM_PREP_NOSYNC 0x04 +#define MSM_PREP_BOOST 0x08 -#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) +#define MSM_PREP_FLAGS (MSM_PREP_READ | \ + MSM_PREP_WRITE | \ + MSM_PREP_NOSYNC | \ + MSM_PREP_BOOST | \ + 0) struct drm_msm_gem_cpu_prep { __u32 handle; /* in */ @@ -286,6 +291,11 @@ struct drm_msm_gem_submit { }; +#define MSM_WAIT_FENCE_BOOST 0x00000001 +#define MSM_WAIT_FENCE_FLAGS ( \ + MSM_WAIT_FENCE_BOOST | \ + 0) + /* The normal way to synchronize with the GPU is just to CPU_PREP on * a buffer if you need to access it from the CPU (other cmdstream * submission from same or other contexts, PAGE_FLIP ioctl, etc, all @@ -295,7 +305,7 @@ struct drm_msm_gem_submit { */ struct drm_msm_wait_fence { __u32 fence; /* in */ - __u32 pad; + __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */ struct drm_msm_timespec timeout; /* in */ __u32 queueid; /* in, submitqueue id */ };