diff mbox series

[v2,2/2] drm/i915: Check for unreliable MMIO during forcewake

Message ID 20230321170936.478631-3-andi.shyti@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series Report MMIO communication problems more clearly | expand

Commit Message

Andi Shyti March 21, 2023, 5:09 p.m. UTC
From: Matt Roper <matthew.d.roper@intel.com>

Although we now sanitycheck MMIO access during driver load to make sure
the MMIO BAR isn't returning all 0xFFFFFFFF, there have been a few cases
where (temporarily?) unreliable MMIO access has happened after GPU
resets or power events.  We'll often notice this on our next GT register
access since forcewake handling will fail; let's change our handling
slightly so that when this happens we print a more meaningful message
clarifying that the problem is the MMIO access, not forcewake
specifically.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

Comments

Andi Shyti March 21, 2023, 5:16 p.m. UTC | #1
> Although we now sanitycheck MMIO access during driver load to make sure
> the MMIO BAR isn't returning all 0xFFFFFFFF, there have been a few cases
> where (temporarily?) unreliable MMIO access has happened after GPU
> resets or power events.  We'll often notice this on our next GT register
> access since forcewake handling will fail; let's change our handling
> slightly so that when this happens we print a more meaningful message
> clarifying that the problem is the MMIO access, not forcewake
> specifically.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Andi
Andrzej Hajda March 22, 2023, 9:10 a.m. UTC | #2
On 21.03.2023 18:09, Andi Shyti wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Although we now sanitycheck MMIO access during driver load to make sure
> the MMIO BAR isn't returning all 0xFFFFFFFF, there have been a few cases
> where (temporarily?) unreliable MMIO access has happened after GPU
> resets or power events.  We'll often notice this on our next GT register
> access since forcewake handling will fail; let's change our handling
> slightly so that when this happens we print a more meaningful message
> clarifying that the problem is the MMIO access, not forcewake
> specifically.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_uncore.c | 12 +++++++++---
>   1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0b69081d6d285..303a5d38c93a5 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -178,9 +178,15 @@ static inline void
>   fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
>   {
>   	if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
> -		drm_err(&d->uncore->i915->drm,
> -			"%s: timed out waiting for forcewake ack to clear.\n",
> -			intel_uncore_forcewake_domain_to_str(d->id));
> +		if (fw_ack(d) == ~0)
> +			drm_err(&d->uncore->i915->drm,
> +				"%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n",
> +				intel_uncore_forcewake_domain_to_str(d->id));
> +		else
> +			drm_err(&d->uncore->i915->drm,
> +				"%s: timed out waiting for forcewake ack to clear.\n",
> +				intel_uncore_forcewake_domain_to_str(d->id));
> +
With:

if (!wait_ack_clear(...))
	return;

you do not need to indent.
And since drm_err have the same set of args in both cases, except fmt, 
it could be also simplified.

Anyway I am not sure if it is worth effort, so:
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej


>   		add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
>   	}
>   }
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0b69081d6d285..303a5d38c93a5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -178,9 +178,15 @@  static inline void
 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 {
 	if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
-		drm_err(&d->uncore->i915->drm,
-			"%s: timed out waiting for forcewake ack to clear.\n",
-			intel_uncore_forcewake_domain_to_str(d->id));
+		if (fw_ack(d) == ~0)
+			drm_err(&d->uncore->i915->drm,
+				"%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n",
+				intel_uncore_forcewake_domain_to_str(d->id));
+		else
+			drm_err(&d->uncore->i915->drm,
+				"%s: timed out waiting for forcewake ack to clear.\n",
+				intel_uncore_forcewake_domain_to_str(d->id));
+
 		add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
 	}
 }