diff mbox series

[v4,5/5] drm/i915/psr: Implement Display WA #1136

Message ID 20230322102204.116056-6-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series High refresh rate PSR fixes | expand

Commit Message

Hogander, Jouni March 22, 2023, 10:22 a.m. UTC 
Implement Display WA #1136 for SKL/BXT.

Bspec: 21664

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c     | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.c |  5 -----
 2 files changed, 17 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b53c71c06105..24c3f75bb9d8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1950,6 +1950,7 @@  void intel_psr_pre_plane_update(struct intel_atomic_state *state,
 /*
  * Wa_16013835468
  * Wa_14015648006
+ * Display WA #1136: skl, bxt
  */
 static void wm_optimization_wa(struct intel_dp *intel_dp,
 			   const struct intel_crtc_state *crtc_state)
@@ -1957,6 +1958,17 @@  static void wm_optimization_wa(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	bool set_wa_bit = false;
 
+	/*
+	 * Display WA #1136: skl, bxt
+	 * skl/bxt do not have chicken bit: disable PSR
+	 */
+	if (DISPLAY_VER(dev_priv) <= 9) {
+		if (crtc_state->wm_level_disabled &&
+		    intel_dp->psr.enabled)
+			intel_psr_disable_locked(intel_dp);
+		return;
+	}
+
 	/* Wa_14015648006 */
 	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
 	    IS_DISPLAY_VER(dev_priv, 11, 13))
@@ -1999,12 +2011,17 @@  static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
 		keep_disabled |= psr->sink_not_reliable;
 		keep_disabled |= !crtc_state->active_planes;
 
+		/* Display WA #1136: skl, bxt */
+		keep_disabled |= DISPLAY_VER(dev_priv) <= 9 &&
+			crtc_state->wm_level_disabled;
+
 		if (!psr->enabled && !keep_disabled)
 			intel_psr_enable_locked(intel_dp, crtc_state);
 
 		/*
 		 * Wa_16013835468
 		 * Wa_14015648006
+		 * Display WA #1136: skl, bxt
 		 */
 		wm_optimization_wa(intel_dp, crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index afb751c024ba..ced61da8b496 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2278,11 +2278,6 @@  static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 	 */
 	crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
 
-	/*
-	 * FIXME also related to skl+ w/a 1136 (also unimplemented as of
-	 * now) perhaps?
-	 */
-
 	for (level++; level < i915->display.wm.num_levels; level++) {
 		enum plane_id plane_id;