| Message ID | 20230322103412.123943-5-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | High refresh rate PSR fixes | expand |
On Wed, Mar 22, 2023 at 12:34:10PM +0200, Jouni Högander wrote: > Add helpers to make it more clear how PSR2_CTL[Block Count Number] > is configured. > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index dfac546d983b..4b7c946a9a25 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -519,6 +519,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) > return val; > } > > +static int psr2_block_count_lines(struct intel_dp *intel_dp) > +{ > + return intel_dp->psr.io_wake_lines < 9 && > + intel_dp->psr.fast_wake_lines < 9 ? 8 : 12; > +} > + > +static int psr2_block_count(struct intel_dp *intel_dp) > +{ > + return psr2_block_count_lines(intel_dp) / 4; > +} > + > static void hsw_activate_psr2(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > @@ -536,11 +547,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= intel_psr2_get_tp_time(intel_dp); > > if (DISPLAY_VER(dev_priv) >= 12) { > - if (intel_dp->psr.io_wake_lines < 9 && > - intel_dp->psr.fast_wake_lines < 9) > - val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; > - else > + if (psr2_block_count(intel_dp) > 2) > val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; > + else > + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; > } > > /* Wa_22012278275:adl-p */ > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index dfac546d983b..4b7c946a9a25 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -519,6 +519,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) return val; } +static int psr2_block_count_lines(struct intel_dp *intel_dp) +{ + return intel_dp->psr.io_wake_lines < 9 && + intel_dp->psr.fast_wake_lines < 9 ? 8 : 12; +} + +static int psr2_block_count(struct intel_dp *intel_dp) +{ + return psr2_block_count_lines(intel_dp) / 4; +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -536,11 +547,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= intel_psr2_get_tp_time(intel_dp); if (DISPLAY_VER(dev_priv) >= 12) { - if (intel_dp->psr.io_wake_lines < 9 && - intel_dp->psr.fast_wake_lines < 9) - val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; - else + if (psr2_block_count(intel_dp) > 2) val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; + else + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; } /* Wa_22012278275:adl-p */
Add helpers to make it more clear how PSR2_CTL[Block Count Number] is configured. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)