| Message ID | 20230323142035.1432621-2-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tc: Align the ADLP TypeC sequences with bspec | expand |
On Thu, 23 Mar 2023, Imre Deak <imre.deak@intel.com> wrote: > Arrange the TC PHY HW state setup/query functions into platform > specific and generic groups. This prepares for upcoming patches adding > generic TC PHY handlers and platform specific hooks for these, > replacing the corresponding if ladders. > > No functional changes. > > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_tc.c | 244 +++++++++++++----------- > 1 file changed, 130 insertions(+), 114 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c > index bd8c9df5f98fe..b6e425c44fcb9 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -15,6 +15,10 @@ > #include "intel_mg_phy_regs.h" > #include "intel_tc.h" > > +static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port); > +static bool tc_phy_status_complete(struct intel_digital_port *dig_port); > +static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take); > + > static const char *tc_port_mode_name(enum tc_port_mode mode) > { > static const char * const names[] = { > @@ -256,6 +260,10 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, > dig_port->tc_legacy_port = !dig_port->tc_legacy_port; > } > > +/** > + * ICL TC PHY handlers > + * ------------------- > + */ These should not be kernel-doc comments, please replace /** with /*. BR, Jani. > static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port) > { > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > @@ -287,44 +295,6 @@ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port) > return mask; > } > > -static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > - u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; > - u32 val, mask = 0; > - > - /* > - * On ADL-P HW/FW will wake from TCCOLD to complete the read access of > - * registers in IOM. Note that this doesn't apply to PHY and FIA > - * registers. > - */ > - val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > - if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) > - mask |= BIT(TC_PORT_DP_ALT); > - if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) > - mask |= BIT(TC_PORT_TBT_ALT); > - > - if (intel_de_read(i915, SDEISR) & isr_bit) > - mask |= BIT(TC_PORT_LEGACY); > - > - /* The sink can be connected only in a single mode. */ > - if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) > - tc_port_fixup_legacy_flag(dig_port, mask); > - > - return mask; > -} > - > -static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - > - if (IS_ALDERLAKE_P(i915)) > - return adl_tc_port_live_status_mask(dig_port); > - > - return icl_tc_port_live_status_mask(dig_port); > -} > - > /* > * Return the PHY status complete flag indicating that display can acquire the > * PHY ownership. The IOM firmware sets this flag when a DP-alt or legacy sink > @@ -349,40 +319,6 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) > return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx); > } > > -/* > - * Return the PHY status complete flag indicating that display can acquire the > - * PHY ownership. The IOM firmware sets this flag when it's ready to switch > - * the ownership to display, regardless of what sink is connected (TBT-alt, > - * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT > - * subsystem and so switching the ownership to display is not required. > - */ > -static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > - u32 val; > - > - val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > - if (val == 0xffffffff) { > - drm_dbg_kms(&i915->drm, > - "Port %s: PHY in TCCOLD, assuming not complete\n", > - dig_port->tc_port_name); > - return false; > - } > - > - return val & TCSS_DDI_STATUS_READY; > -} > - > -static bool tc_phy_status_complete(struct intel_digital_port *dig_port) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - > - if (IS_ALDERLAKE_P(i915)) > - return adl_tc_phy_status_complete(dig_port); > - > - return icl_tc_phy_status_complete(dig_port); > -} > - > static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port, > bool take) > { > @@ -407,28 +343,6 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port, > return true; > } > > -static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, > - bool take) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - enum port port = dig_port->base.port; > - > - intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP, > - take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0); > - > - return true; > -} > - > -static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - > - if (IS_ALDERLAKE_P(i915)) > - return adl_tc_phy_take_ownership(dig_port, take); > - > - return icl_tc_phy_take_ownership(dig_port, take); > -} > - > static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port) > { > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > @@ -445,26 +359,6 @@ static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port) > return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); > } > > -static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - enum port port = dig_port->base.port; > - u32 val; > - > - val = intel_de_read(i915, DDI_BUF_CTL(port)); > - return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; > -} > - > -static bool tc_phy_is_owned(struct intel_digital_port *dig_port) > -{ > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > - > - if (IS_ALDERLAKE_P(i915)) > - return adl_tc_phy_is_owned(dig_port); > - > - return icl_tc_phy_is_owned(dig_port); > -} > - > /* > * This function implements the first part of the Connect Flow described by our > * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading > @@ -559,6 +453,128 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port) > } > } > > +/** > + * ADLP TC PHY handlers > + * -------------------- > + */ > +static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > + u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; > + u32 val, mask = 0; > + > + /* > + * On ADL-P HW/FW will wake from TCCOLD to complete the read access of > + * registers in IOM. Note that this doesn't apply to PHY and FIA > + * registers. > + */ > + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > + if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) > + mask |= BIT(TC_PORT_DP_ALT); > + if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) > + mask |= BIT(TC_PORT_TBT_ALT); > + > + if (intel_de_read(i915, SDEISR) & isr_bit) > + mask |= BIT(TC_PORT_LEGACY); > + > + /* The sink can be connected only in a single mode. */ > + if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) > + tc_port_fixup_legacy_flag(dig_port, mask); > + > + return mask; > +} > + > +/* > + * Return the PHY status complete flag indicating that display can acquire the > + * PHY ownership. The IOM firmware sets this flag when it's ready to switch > + * the ownership to display, regardless of what sink is connected (TBT-alt, > + * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT > + * subsystem and so switching the ownership to display is not required. > + */ > +static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > + u32 val; > + > + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > + if (val == 0xffffffff) { > + drm_dbg_kms(&i915->drm, > + "Port %s: PHY in TCCOLD, assuming not complete\n", > + dig_port->tc_port_name); > + return false; > + } > + > + return val & TCSS_DDI_STATUS_READY; > +} > + > +static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, > + bool take) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + enum port port = dig_port->base.port; > + > + intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP, > + take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0); > + > + return true; > +} > + > +static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + enum port port = dig_port->base.port; > + u32 val; > + > + val = intel_de_read(i915, DDI_BUF_CTL(port)); > + return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; > +} > + > +/** > + * Generic TC PHY handlers > + * ----------------------- > + */ > +static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + > + if (IS_ALDERLAKE_P(i915)) > + return adl_tc_port_live_status_mask(dig_port); > + > + return icl_tc_port_live_status_mask(dig_port); > +} > + > +static bool tc_phy_status_complete(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + > + if (IS_ALDERLAKE_P(i915)) > + return adl_tc_phy_status_complete(dig_port); > + > + return icl_tc_phy_status_complete(dig_port); > +} > + > +static bool tc_phy_is_owned(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + > + if (IS_ALDERLAKE_P(i915)) > + return adl_tc_phy_is_owned(dig_port); > + > + return icl_tc_phy_is_owned(dig_port); > +} > + > +static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + > + if (IS_ALDERLAKE_P(i915)) > + return adl_tc_phy_take_ownership(dig_port, take); > + > + return icl_tc_phy_take_ownership(dig_port, take); > +} > + > static bool tc_phy_is_ready_and_owned(struct intel_digital_port *dig_port, > bool phy_is_ready, bool phy_is_owned) > {
Hi Imre,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-i915-tc-Group-the-TC-PHY-setup-query-functions-per-platform/20230323-222328
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230323142035.1432621-2-imre.deak%40intel.com
patch subject: [Intel-gfx] [PATCH 01/29] drm/i915/tc: Group the TC PHY setup/query functions per platform
config: x86_64-randconfig-a005 (https://download.01.org/0day-ci/archive/20230324/202303240014.FNfWYmf7-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/7b85ed1627f7c16b7ff080b604d35d729c70313f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Imre-Deak/drm-i915-tc-Group-the-TC-PHY-setup-query-functions-per-platform/20230323-222328
git checkout 7b85ed1627f7c16b7ff080b604d35d729c70313f
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303240014.FNfWYmf7-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_tc.c:264: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* ICL TC PHY handlers
drivers/gpu/drm/i915/display/intel_tc.c:457: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* ADLP TC PHY handlers
drivers/gpu/drm/i915/display/intel_tc.c:535: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Generic TC PHY handlers
drivers/gpu/drm/i915/display/intel_tc.c:1026: warning: Function parameter or member 'work' not described in 'intel_tc_port_disconnect_phy_work'
drivers/gpu/drm/i915/display/intel_tc.c:1026: warning: Excess function parameter 'dig_port' description in 'intel_tc_port_disconnect_phy_work'
vim +264 drivers/gpu/drm/i915/display/intel_tc.c
262
263 /**
> 264 * ICL TC PHY handlers
265 * -------------------
266 */
267 static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
268 {
269 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
270 u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
271 u32 mask = 0;
272 u32 val;
273
274 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
275
276 if (val == 0xffffffff) {
277 drm_dbg_kms(&i915->drm,
278 "Port %s: PHY in TCCOLD, nothing connected\n",
279 dig_port->tc_port_name);
280 return mask;
281 }
282
283 if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
284 mask |= BIT(TC_PORT_TBT_ALT);
285 if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
286 mask |= BIT(TC_PORT_DP_ALT);
287
288 if (intel_de_read(i915, SDEISR) & isr_bit)
289 mask |= BIT(TC_PORT_LEGACY);
290
291 /* The sink can be connected only in a single mode. */
292 if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1))
293 tc_port_fixup_legacy_flag(dig_port, mask);
294
295 return mask;
296 }
297
Hi Imre,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-i915-tc-Group-the-TC-PHY-setup-query-functions-per-platform/20230323-222328
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230323142035.1432621-2-imre.deak%40intel.com
patch subject: [Intel-gfx] [PATCH 01/29] drm/i915/tc: Group the TC PHY setup/query functions per platform
config: i386-randconfig-a004 (https://download.01.org/0day-ci/archive/20230324/202303240020.UQr6flaJ-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/7b85ed1627f7c16b7ff080b604d35d729c70313f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Imre-Deak/drm-i915-tc-Group-the-TC-PHY-setup-query-functions-per-platform/20230323-222328
git checkout 7b85ed1627f7c16b7ff080b604d35d729c70313f
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303240020.UQr6flaJ-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_tc.c:264: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* ICL TC PHY handlers
drivers/gpu/drm/i915/display/intel_tc.c:457: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* ADLP TC PHY handlers
drivers/gpu/drm/i915/display/intel_tc.c:535: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Generic TC PHY handlers
drivers/gpu/drm/i915/display/intel_tc.c:1026: warning: Function parameter or member 'work' not described in 'intel_tc_port_disconnect_phy_work'
drivers/gpu/drm/i915/display/intel_tc.c:1026: warning: Excess function parameter 'dig_port' description in 'intel_tc_port_disconnect_phy_work'
vim +264 drivers/gpu/drm/i915/display/intel_tc.c
262
263 /**
> 264 * ICL TC PHY handlers
265 * -------------------
266 */
267 static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
268 {
269 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
270 u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
271 u32 mask = 0;
272 u32 val;
273
274 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
275
276 if (val == 0xffffffff) {
277 drm_dbg_kms(&i915->drm,
278 "Port %s: PHY in TCCOLD, nothing connected\n",
279 dig_port->tc_port_name);
280 return mask;
281 }
282
283 if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
284 mask |= BIT(TC_PORT_TBT_ALT);
285 if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
286 mask |= BIT(TC_PORT_DP_ALT);
287
288 if (intel_de_read(i915, SDEISR) & isr_bit)
289 mask |= BIT(TC_PORT_LEGACY);
290
291 /* The sink can be connected only in a single mode. */
292 if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1))
293 tc_port_fixup_legacy_flag(dig_port, mask);
294
295 return mask;
296 }
297
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani > Nikula > Sent: Thursday, March 23, 2023 4:33 PM > To: Deak, Imre <imre.deak@intel.com>; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 01/29] drm/i915/tc: Group the TC PHY > setup/query functions per platform > > On Thu, 23 Mar 2023, Imre Deak <imre.deak@intel.com> wrote: > > Arrange the TC PHY HW state setup/query functions into platform > > specific and generic groups. This prepares for upcoming patches adding > > generic TC PHY handlers and platform specific hooks for these, > > replacing the corresponding if ladders. > > > > No functional changes. > > With the kernel doc comments fixed, this is Reviewed-by: Mika Kahola <mika.kahola@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_tc.c | 244 > > +++++++++++++----------- > > 1 file changed, 130 insertions(+), 114 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c > > b/drivers/gpu/drm/i915/display/intel_tc.c > > index bd8c9df5f98fe..b6e425c44fcb9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_tc.c > > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > > @@ -15,6 +15,10 @@ > > #include "intel_mg_phy_regs.h" > > #include "intel_tc.h" > > > > +static u32 tc_port_live_status_mask(struct intel_digital_port > > +*dig_port); static bool tc_phy_status_complete(struct > > +intel_digital_port *dig_port); static bool > > +tc_phy_take_ownership(struct intel_digital_port *dig_port, bool > > +take); > > + > > static const char *tc_port_mode_name(enum tc_port_mode mode) { > > static const char * const names[] = { @@ -256,6 +260,10 @@ static > > void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, > > dig_port->tc_legacy_port = !dig_port->tc_legacy_port; } > > > > +/** > > + * ICL TC PHY handlers > > + * ------------------- > > + */ > > These should not be kernel-doc comments, please replace /** with /*. > > BR, > Jani. > > > > > static u32 icl_tc_port_live_status_mask(struct intel_digital_port > > *dig_port) { > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ > > -287,44 +295,6 @@ static u32 icl_tc_port_live_status_mask(struct > intel_digital_port *dig_port) > > return mask; > > } > > > > -static u32 adl_tc_port_live_status_mask(struct intel_digital_port > > *dig_port) -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > > - u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; > > - u32 val, mask = 0; > > - > > - /* > > - * On ADL-P HW/FW will wake from TCCOLD to complete the read > access of > > - * registers in IOM. Note that this doesn't apply to PHY and FIA > > - * registers. > > - */ > > - val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > > - if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) > > - mask |= BIT(TC_PORT_DP_ALT); > > - if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) > > - mask |= BIT(TC_PORT_TBT_ALT); > > - > > - if (intel_de_read(i915, SDEISR) & isr_bit) > > - mask |= BIT(TC_PORT_LEGACY); > > - > > - /* The sink can be connected only in a single mode. */ > > - if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) > > - tc_port_fixup_legacy_flag(dig_port, mask); > > - > > - return mask; > > -} > > - > > -static u32 tc_port_live_status_mask(struct intel_digital_port > > *dig_port) -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - > > - if (IS_ALDERLAKE_P(i915)) > > - return adl_tc_port_live_status_mask(dig_port); > > - > > - return icl_tc_port_live_status_mask(dig_port); > > -} > > - > > /* > > * Return the PHY status complete flag indicating that display can acquire the > > * PHY ownership. The IOM firmware sets this flag when a DP-alt or > > legacy sink @@ -349,40 +319,6 @@ static bool > icl_tc_phy_status_complete(struct intel_digital_port *dig_port) > > return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port- > >tc_phy_fia_idx); > > } > > > > -/* > > - * Return the PHY status complete flag indicating that display can > > acquire the > > - * PHY ownership. The IOM firmware sets this flag when it's ready to > > switch > > - * the ownership to display, regardless of what sink is connected > > (TBT-alt, > > - * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by > > the TBT > > - * subsystem and so switching the ownership to display is not required. > > - */ > > -static bool adl_tc_phy_status_complete(struct intel_digital_port > > *dig_port) -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > > - u32 val; > > - > > - val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > > - if (val == 0xffffffff) { > > - drm_dbg_kms(&i915->drm, > > - "Port %s: PHY in TCCOLD, assuming not complete\n", > > - dig_port->tc_port_name); > > - return false; > > - } > > - > > - return val & TCSS_DDI_STATUS_READY; > > -} > > - > > -static bool tc_phy_status_complete(struct intel_digital_port > > *dig_port) -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - > > - if (IS_ALDERLAKE_P(i915)) > > - return adl_tc_phy_status_complete(dig_port); > > - > > - return icl_tc_phy_status_complete(dig_port); > > -} > > - > > static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port, > > bool take) > > { > > @@ -407,28 +343,6 @@ static bool icl_tc_phy_take_ownership(struct > intel_digital_port *dig_port, > > return true; > > } > > > > -static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, > > - bool take) > > -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - enum port port = dig_port->base.port; > > - > > - intel_de_rmw(i915, DDI_BUF_CTL(port), > DDI_BUF_CTL_TC_PHY_OWNERSHIP, > > - take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0); > > - > > - return true; > > -} > > - > > -static bool tc_phy_take_ownership(struct intel_digital_port > > *dig_port, bool take) -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - > > - if (IS_ALDERLAKE_P(i915)) > > - return adl_tc_phy_take_ownership(dig_port, take); > > - > > - return icl_tc_phy_take_ownership(dig_port, take); > > -} > > - > > static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port) > > { > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ > > -445,26 +359,6 @@ static bool icl_tc_phy_is_owned(struct intel_digital_port > *dig_port) > > return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port- > >tc_phy_fia_idx); > > } > > > > -static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) > > -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - enum port port = dig_port->base.port; > > - u32 val; > > - > > - val = intel_de_read(i915, DDI_BUF_CTL(port)); > > - return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; > > -} > > - > > -static bool tc_phy_is_owned(struct intel_digital_port *dig_port) -{ > > - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > - > > - if (IS_ALDERLAKE_P(i915)) > > - return adl_tc_phy_is_owned(dig_port); > > - > > - return icl_tc_phy_is_owned(dig_port); > > -} > > - > > /* > > * This function implements the first part of the Connect Flow described by our > > * specification, Gen11 TypeC Programming chapter. The rest of the > > flow (reading @@ -559,6 +453,128 @@ static void > icl_tc_phy_disconnect(struct intel_digital_port *dig_port) > > } > > } > > > > +/** > > + * ADLP TC PHY handlers > > + * -------------------- > > + */ > > +static u32 adl_tc_port_live_status_mask(struct intel_digital_port > > +*dig_port) { > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > > + u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; > > + u32 val, mask = 0; > > + > > + /* > > + * On ADL-P HW/FW will wake from TCCOLD to complete the read > access of > > + * registers in IOM. Note that this doesn't apply to PHY and FIA > > + * registers. > > + */ > > + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > > + if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) > > + mask |= BIT(TC_PORT_DP_ALT); > > + if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) > > + mask |= BIT(TC_PORT_TBT_ALT); > > + > > + if (intel_de_read(i915, SDEISR) & isr_bit) > > + mask |= BIT(TC_PORT_LEGACY); > > + > > + /* The sink can be connected only in a single mode. */ > > + if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) > > + tc_port_fixup_legacy_flag(dig_port, mask); > > + > > + return mask; > > +} > > + > > +/* > > + * Return the PHY status complete flag indicating that display can > > +acquire the > > + * PHY ownership. The IOM firmware sets this flag when it's ready to > > +switch > > + * the ownership to display, regardless of what sink is connected > > +(TBT-alt, > > + * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by > > +the TBT > > + * subsystem and so switching the ownership to display is not required. > > + */ > > +static bool adl_tc_phy_status_complete(struct intel_digital_port > > +*dig_port) { > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); > > + u32 val; > > + > > + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); > > + if (val == 0xffffffff) { > > + drm_dbg_kms(&i915->drm, > > + "Port %s: PHY in TCCOLD, assuming not complete\n", > > + dig_port->tc_port_name); > > + return false; > > + } > > + > > + return val & TCSS_DDI_STATUS_READY; > > +} > > + > > +static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, > > + bool take) > > +{ > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + enum port port = dig_port->base.port; > > + > > + intel_de_rmw(i915, DDI_BUF_CTL(port), > DDI_BUF_CTL_TC_PHY_OWNERSHIP, > > + take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0); > > + > > + return true; > > +} > > + > > +static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) > > +{ > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + enum port port = dig_port->base.port; > > + u32 val; > > + > > + val = intel_de_read(i915, DDI_BUF_CTL(port)); > > + return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; } > > + > > +/** > > + * Generic TC PHY handlers > > + * ----------------------- > > + */ > > +static u32 tc_port_live_status_mask(struct intel_digital_port > > +*dig_port) { > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + > > + if (IS_ALDERLAKE_P(i915)) > > + return adl_tc_port_live_status_mask(dig_port); > > + > > + return icl_tc_port_live_status_mask(dig_port); > > +} > > + > > +static bool tc_phy_status_complete(struct intel_digital_port > > +*dig_port) { > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + > > + if (IS_ALDERLAKE_P(i915)) > > + return adl_tc_phy_status_complete(dig_port); > > + > > + return icl_tc_phy_status_complete(dig_port); > > +} > > + > > +static bool tc_phy_is_owned(struct intel_digital_port *dig_port) { > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + > > + if (IS_ALDERLAKE_P(i915)) > > + return adl_tc_phy_is_owned(dig_port); > > + > > + return icl_tc_phy_is_owned(dig_port); } > > + > > +static bool tc_phy_take_ownership(struct intel_digital_port > > +*dig_port, bool take) { > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + > > + if (IS_ALDERLAKE_P(i915)) > > + return adl_tc_phy_take_ownership(dig_port, take); > > + > > + return icl_tc_phy_take_ownership(dig_port, take); } > > + > > static bool tc_phy_is_ready_and_owned(struct intel_digital_port *dig_port, > > bool phy_is_ready, bool phy_is_owned) { > > -- > Jani Nikula, Intel Open Source Graphics Center
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index bd8c9df5f98fe..b6e425c44fcb9 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -15,6 +15,10 @@ #include "intel_mg_phy_regs.h" #include "intel_tc.h" +static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port); +static bool tc_phy_status_complete(struct intel_digital_port *dig_port); +static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take); + static const char *tc_port_mode_name(enum tc_port_mode mode) { static const char * const names[] = { @@ -256,6 +260,10 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port, dig_port->tc_legacy_port = !dig_port->tc_legacy_port; } +/** + * ICL TC PHY handlers + * ------------------- + */ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -287,44 +295,6 @@ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port) return mask; } -static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); - u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; - u32 val, mask = 0; - - /* - * On ADL-P HW/FW will wake from TCCOLD to complete the read access of - * registers in IOM. Note that this doesn't apply to PHY and FIA - * registers. - */ - val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); - if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) - mask |= BIT(TC_PORT_DP_ALT); - if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) - mask |= BIT(TC_PORT_TBT_ALT); - - if (intel_de_read(i915, SDEISR) & isr_bit) - mask |= BIT(TC_PORT_LEGACY); - - /* The sink can be connected only in a single mode. */ - if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) - tc_port_fixup_legacy_flag(dig_port, mask); - - return mask; -} - -static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - - if (IS_ALDERLAKE_P(i915)) - return adl_tc_port_live_status_mask(dig_port); - - return icl_tc_port_live_status_mask(dig_port); -} - /* * Return the PHY status complete flag indicating that display can acquire the * PHY ownership. The IOM firmware sets this flag when a DP-alt or legacy sink @@ -349,40 +319,6 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx); } -/* - * Return the PHY status complete flag indicating that display can acquire the - * PHY ownership. The IOM firmware sets this flag when it's ready to switch - * the ownership to display, regardless of what sink is connected (TBT-alt, - * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT - * subsystem and so switching the ownership to display is not required. - */ -static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); - u32 val; - - val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); - if (val == 0xffffffff) { - drm_dbg_kms(&i915->drm, - "Port %s: PHY in TCCOLD, assuming not complete\n", - dig_port->tc_port_name); - return false; - } - - return val & TCSS_DDI_STATUS_READY; -} - -static bool tc_phy_status_complete(struct intel_digital_port *dig_port) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - - if (IS_ALDERLAKE_P(i915)) - return adl_tc_phy_status_complete(dig_port); - - return icl_tc_phy_status_complete(dig_port); -} - static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take) { @@ -407,28 +343,6 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port, return true; } -static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, - bool take) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - enum port port = dig_port->base.port; - - intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP, - take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0); - - return true; -} - -static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - - if (IS_ALDERLAKE_P(i915)) - return adl_tc_phy_take_ownership(dig_port, take); - - return icl_tc_phy_take_ownership(dig_port, take); -} - static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -445,26 +359,6 @@ static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port) return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx); } -static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - enum port port = dig_port->base.port; - u32 val; - - val = intel_de_read(i915, DDI_BUF_CTL(port)); - return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; -} - -static bool tc_phy_is_owned(struct intel_digital_port *dig_port) -{ - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); - - if (IS_ALDERLAKE_P(i915)) - return adl_tc_phy_is_owned(dig_port); - - return icl_tc_phy_is_owned(dig_port); -} - /* * This function implements the first part of the Connect Flow described by our * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading @@ -559,6 +453,128 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port) } } +/** + * ADLP TC PHY handlers + * -------------------- + */ +static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); + u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; + u32 val, mask = 0; + + /* + * On ADL-P HW/FW will wake from TCCOLD to complete the read access of + * registers in IOM. Note that this doesn't apply to PHY and FIA + * registers. + */ + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); + if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT) + mask |= BIT(TC_PORT_DP_ALT); + if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT) + mask |= BIT(TC_PORT_TBT_ALT); + + if (intel_de_read(i915, SDEISR) & isr_bit) + mask |= BIT(TC_PORT_LEGACY); + + /* The sink can be connected only in a single mode. */ + if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) + tc_port_fixup_legacy_flag(dig_port, mask); + + return mask; +} + +/* + * Return the PHY status complete flag indicating that display can acquire the + * PHY ownership. The IOM firmware sets this flag when it's ready to switch + * the ownership to display, regardless of what sink is connected (TBT-alt, + * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT + * subsystem and so switching the ownership to display is not required. + */ +static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); + u32 val; + + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); + if (val == 0xffffffff) { + drm_dbg_kms(&i915->drm, + "Port %s: PHY in TCCOLD, assuming not complete\n", + dig_port->tc_port_name); + return false; + } + + return val & TCSS_DDI_STATUS_READY; +} + +static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, + bool take) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + enum port port = dig_port->base.port; + + intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP, + take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0); + + return true; +} + +static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + enum port port = dig_port->base.port; + u32 val; + + val = intel_de_read(i915, DDI_BUF_CTL(port)); + return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; +} + +/** + * Generic TC PHY handlers + * ----------------------- + */ +static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + if (IS_ALDERLAKE_P(i915)) + return adl_tc_port_live_status_mask(dig_port); + + return icl_tc_port_live_status_mask(dig_port); +} + +static bool tc_phy_status_complete(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + if (IS_ALDERLAKE_P(i915)) + return adl_tc_phy_status_complete(dig_port); + + return icl_tc_phy_status_complete(dig_port); +} + +static bool tc_phy_is_owned(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + if (IS_ALDERLAKE_P(i915)) + return adl_tc_phy_is_owned(dig_port); + + return icl_tc_phy_is_owned(dig_port); +} + +static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + if (IS_ALDERLAKE_P(i915)) + return adl_tc_phy_take_ownership(dig_port, take); + + return icl_tc_phy_take_ownership(dig_port, take); +} + static bool tc_phy_is_ready_and_owned(struct intel_digital_port *dig_port, bool phy_is_ready, bool phy_is_owned) {
Arrange the TC PHY HW state setup/query functions into platform specific and generic groups. This prepares for upcoming patches adding generic TC PHY handlers and platform specific hooks for these, replacing the corresponding if ladders. No functional changes. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_tc.c | 244 +++++++++++++----------- 1 file changed, 130 insertions(+), 114 deletions(-)