| Message ID | 20230323142035.1432621-7-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tc: Align the ADLP TypeC sequences with bspec | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre > Deak > Sent: Thursday, March 23, 2023 4:20 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 06/29] drm/i915/tc: Check for TC PHY explicitly in > intel_tc_port_fia_max_lane_count() > > Check explicitly if the port passed to > intel_tc_port_fia_max_lane_count() has a TC PHY, instead of relying on the > default TC mode value set for non-TC PHY ports. > Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_tc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c > b/drivers/gpu/drm/i915/display/intel_tc.c > index 70771044a2fe8..48a59a675cd57 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -188,10 +188,11 @@ int intel_tc_port_fia_max_lane_count(struct > intel_digital_port *dig_port) { > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > struct intel_tc_port *tc = to_tc_port(dig_port); > + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); > intel_wakeref_t wakeref; > u32 lane_mask; > > - if (tc->mode != TC_PORT_DP_ALT) > + if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT) > return 4; > > assert_tc_cold_blocked(tc); > -- > 2.37.1
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 70771044a2fe8..48a59a675cd57 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -188,10 +188,11 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); struct intel_tc_port *tc = to_tc_port(dig_port); + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); intel_wakeref_t wakeref; u32 lane_mask; - if (tc->mode != TC_PORT_DP_ALT) + if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT) return 4; assert_tc_cold_blocked(tc);
Check explicitly if the port passed to intel_tc_port_fia_max_lane_count() has a TC PHY, instead of relying on the default TC mode value set for non-TC PHY ports. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_tc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)