@@ -116,6 +116,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
}
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
@@ -1601,6 +1602,39 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static int
+intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int max_bpc)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+ int req_rate_gbps;
+ int max_frl_rate = connector->display_info.hdmi.max_lanes *
+ connector->display_info.hdmi.max_frl_rate_per_lane;
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ if (dsc_bpc[i] > max_bpc)
+ continue;
+
+ req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000);
+
+ /* YCBCR420 reduces data rate by 2 */
+ if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ req_rate_gbps /= 2;
+
+ if (req_rate_gbps < max_frl_rate)
+ return dsc_bpc[i] * 3;
+ }
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1609,6 +1643,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
bool compute_pipe_bpp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -1620,11 +1656,30 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
-
- if (compute_pipe_bpp)
+ /*
+ * In cases where PCON with HDMI2.1 as branch device, if PCON supports
+ * DSC but HDMI2.1 sink does not supports DSC, there can be issues due
+ * to the bpc used.
+ * With DSC, a source-PCON pair can support the mode with higher bpcs.
+ * But PCON->Sink pair, cannot support the same bpc without sink having
+ * DSC support.
+ * So use the max BPC as input BPC that will be sufficient to show the
+ * mode without DSC from PCON->HDMI2.1
+ */
+ if (intel_dp_is_hdmi_2_1_sink(intel_dp) &&
+ !connector->display_info.hdmi.dsc_cap.v_1p2) {
+ pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config,
+ conn_state->max_requested_bpc);
+ if (!pipe_bpp) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No BPC possible to support the mode without HDMI2.1 DSC\n");
+ return -EINVAL;
+ }
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
+ }
if (intel_dp->force_dsc_bpc) {
pipe_bpp = intel_dp->force_dsc_bpc * 3;
Currently we use the highest input BPC supported by DP sink while using DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same input BPC that is used between Source and the PCON without DSC, which might not work even with the maximum FRL rate supported by HDMI2.1 sink. This patch calculates the max BPC that can be sufficient with either RGB or YCBCR420 format for the maximum FRL rate supported. v2: Rebase v3: Use the sink_format in the functions instead of ycbcr420 flag. v4: Rebase Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 61 +++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 3 deletions(-)