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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w5-20020ac25985000000b004e844bb6939sm1680666lfn.2.2023.04.03.02.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 02:23:21 -0700 (PDT) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Suraj Kandpal , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Date: Mon, 3 Apr 2023 12:23:12 +0300 Message-Id: <20230403092313.235320-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230403092313.235320-1-dmitry.baryshkov@linaro.org> References: <20230403092313.235320-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 11/12] drm/i915/dsc: use additional DSC helpers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, intel-gfx@lists.freedesktop.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Switch to drm_dsc_set_const_params() to set some semi-constant parameters. The rc_model_size, which is set beforehand, is preserved by the helper. Also make use of drm_dsc_set_initial_scale_value(). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/i915/display/intel_vdsc.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index bd9116d2cd76..2d4917ca1f14 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -216,6 +216,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; + drm_dsc_set_const_params(vdsc_cfg); drm_dsc_set_rc_buf_thresh(vdsc_cfg); /* @@ -251,19 +252,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->rc_range_params[0].range_bpg_offset = 0; } - /* - * BitsPerComponent value determines mux_word_size: - * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to - * 48 bits otherwise 64 - */ - if (vdsc_cfg->bits_per_component <= 10) - vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; - else - vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; - - /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ - vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / - (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); + drm_dsc_set_initial_scale_value(vdsc_cfg); return 0; }