From patchwork Tue Apr 4 10:13:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kalvala, Haridhar" X-Patchwork-Id: 13199453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDB79C6FD1D for ; Tue, 4 Apr 2023 10:15:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 62DDE10E029; Tue, 4 Apr 2023 10:15:12 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id B5E5D10E63E for ; Tue, 4 Apr 2023 10:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680603310; x=1712139310; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=dnVlIVRoGbmir80fpBVTdDdmqPDrMJ5xDSSjUy+VZ60=; b=TN00/1X87opWGgsIr7gdk3CXVXLFXjyK5XpgKW+/4UJ9aCeqd8dZOdlO w/2T387cp5p4TpGFOpEb5sk6tCOQVouHn5bfsaMjd386Wg3V7eyDrmcm/ Ii8/AfwSHzESCD8tWaCH5fLzKr9frgjcHaASGp03n/ok0Y0cyMsgSEJoG j5+n5PBSNLkortKscfY6M9lbvh4YJSWThjXj3aEjv7hZHbN9680gHtnpW tXngnIGcwk2ePgmipqjN9rE+4OQEFnBMmeMgLfqLeD6MFcMqA66buz1P2 /BndxEptEdDoxdlzZpuUemHtKI7nCfKo75oaoIKbpfXUwfjmDZNgzMj3W A==; X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="340872802" X-IronPort-AV: E=Sophos;i="5.98,317,1673942400"; d="scan'208";a="340872802" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 03:15:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="860544742" X-IronPort-AV: E=Sophos;i="5.98,317,1673942400"; d="scan'208";a="860544742" Received: from haridhar-ms-7d25.iind.intel.com ([10.190.238.92]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 03:15:08 -0700 From: Haridhar Kalvala To: intel-gfx@lists.freedesktop.org Date: Tue, 4 Apr 2023 15:43:10 +0530 Message-Id: <20230404101310.3143519-1-haridhar.kalvala@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client] drm/i915/mtl: Add Wa_14017856879 for mtl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com, balasubramani.vivekanandan@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Wa_14017856879 implementation for mtl. Bspec: 46046 Signed-off-by: Haridhar Kalvala --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 35a4cfac2d20..492b3de6678d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1177,7 +1177,9 @@ #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) +#define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) +#define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9) #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) #define FLOW_CONTROL_ENABLE REG_BIT(15) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 1c8e0e91a2fe..6ea453ddd011 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2971,6 +2971,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li add_render_compute_tuning_settings(i915, wal); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) + /* Wa_14017856879 */ + wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) /*