| Message ID | 20230404173220.3175577-1-haridhar.kalvala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Add Wa_14017856879 | expand |
Quoting Haridhar Kalvala (2023-04-04 14:32:20) > Wa_14017856879 implementation for mtl. > > Bspec: 46046 > > Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 35a4cfac2d20..492b3de6678d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1177,7 +1177,9 @@ > #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > +#define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c) > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > +#define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9) > > #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) > #define FLOW_CONTROL_ENABLE REG_BIT(15) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 1c8e0e91a2fe..6ea453ddd011 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2971,6 +2971,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > add_render_compute_tuning_settings(i915, wal); > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) > + /* Wa_14017856879 */ > + wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); > + > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) > /* > -- > 2.25.1 >
On Tue, Apr 04, 2023 at 03:29:15PM -0300, Gustavo Sousa wrote: > Quoting Haridhar Kalvala (2023-04-04 14:32:20) > > Wa_14017856879 implementation for mtl. > > > > Bspec: 46046 > > > > Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> > > Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Applied to drm-intel-gt-next. Thanks for the patch and review. Matt > > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > > 2 files changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 35a4cfac2d20..492b3de6678d 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -1177,7 +1177,9 @@ > > #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) > > > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > > +#define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c) > > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > > +#define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9) > > > > #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) > > #define FLOW_CONTROL_ENABLE REG_BIT(15) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 1c8e0e91a2fe..6ea453ddd011 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -2971,6 +2971,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > > > add_render_compute_tuning_settings(i915, wal); > > > > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || > > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) > > + /* Wa_14017856879 */ > > + wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); > > + > > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) > > /* > > -- > > 2.25.1 > >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 35a4cfac2d20..492b3de6678d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1177,7 +1177,9 @@ #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) +#define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) +#define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9) #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) #define FLOW_CONTROL_ENABLE REG_BIT(15) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 1c8e0e91a2fe..6ea453ddd011 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2971,6 +2971,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li add_render_compute_tuning_settings(i915, wal); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) + /* Wa_14017856879 */ + wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) /*
Wa_14017856879 implementation for mtl. Bspec: 46046 Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ 2 files changed, 7 insertions(+)