diff mbox series

[v2,7/8] drm/i915/psr: Include PSR_PERF_CNT in debugfs output on all platforms

Message ID 20230411191429.29895-8-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: (mostly) PSR related register cleanups | expand

Commit Message

Ville Syrjälä April 11, 2023, 7:14 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 28817f7bd8c3..843fec3651e0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2872,12 +2872,10 @@  static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 	/*
 	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
 	 */
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		val = intel_de_read(dev_priv,
-				    EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
-		seq_printf(m, "Performance counter: %u\n",
-			   REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));
-	}
+	val = intel_de_read(dev_priv,
+			    EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
+	seq_printf(m, "Performance counter: %u\n",
+		   REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));
 
 	if (psr->debug & I915_PSR_DEBUG_IRQ) {
 		seq_printf(m, "Last attempted entry at: %lld\n",