diff mbox series

drm/i915/mtl: Add workaround 14018778641

Message ID 20230420112123.3486469-1-tejas.upadhyay@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/mtl: Add workaround 14018778641 | expand

Commit Message

Upadhyay, Tejas April 20, 2023, 11:21 a.m. UTC 
WA 18018781329 is applicable now across all MTL
steppings.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

Comments

Nirmoy Das April 20, 2023, 11:45 a.m. UTC | #1 
On 4/20/2023 1:21 PM, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>


Acked-by: Nirmoy Das <nirmoy.das@intel.com>

> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++++-------
>   1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 312eb8b5f949..c73d2b5410d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1695,17 +1695,22 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   static void
>   xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   {
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> -		/* Wa_14014830051 */
> -		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> +	/* Wa_14018778641: MTL */
> +	if (IS_METEORLAKE(gt->i915)) {
>   
>   		/* Wa_18018781329 */
>   		wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
>   		wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>   
> -		/* Wa_14015795083 */
> -		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> +		if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +		    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> +			/* Wa_14014830051 */
> +			wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> +
> +			/* Wa_14015795083 */
> +			wa_write_clr(wal, GEN7_MISCCPCTL,
> +				     GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> +		}
>   	}
>   
>   	/*
> @@ -1718,7 +1723,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   static void
>   xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   {
> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) {
> +	/* Wa_14018778641: MTL */
> +	if (IS_METEORLAKE(gt->i915)) {
>   		/*
>   		 * Wa_18018781329
>   		 *
Matt Roper April 21, 2023, midnight UTC | #2 
On Thu, Apr 20, 2023 at 04:51:23PM +0530, Tejas Upadhyay wrote:
> WA 18018781329 is applicable now across all MTL
> steppings.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 312eb8b5f949..c73d2b5410d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1695,17 +1695,22 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  static void
>  xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> -		/* Wa_14014830051 */
> -		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> +	/* Wa_14018778641: MTL */
> +	if (IS_METEORLAKE(gt->i915)) {

It's already MTL if we're inside this function.  No need for the
condition.  Same for the one in xelpmp_gt_workarounds_init farther down.

In the future it's possible that other platforms could re-use the Xe_LPG
and/or Xe_LPM+ chips in a different platform.  If that happens, we'd
also want these workarounds to apply on those other non-MTL platforms as
well since the workaround is tied to the IP rather than the platform.


Matt

>  
>  		/* Wa_18018781329 */
>  		wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
>  		wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>  
> -		/* Wa_14015795083 */
> -		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> +		if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +		    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> +			/* Wa_14014830051 */
> +			wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> +
> +			/* Wa_14015795083 */
> +			wa_write_clr(wal, GEN7_MISCCPCTL,
> +				     GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> +		}
>  	}
>  
>  	/*
> @@ -1718,7 +1723,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  static void
>  xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
> -	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) {
> +	/* Wa_14018778641: MTL */
> +	if (IS_METEORLAKE(gt->i915)) {
>  		/*
>  		 * Wa_18018781329
>  		 *
> -- 
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 312eb8b5f949..c73d2b5410d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1695,17 +1695,22 @@  pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 static void
 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
-		/* Wa_14014830051 */
-		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
+	/* Wa_14018778641: MTL */
+	if (IS_METEORLAKE(gt->i915)) {
 
 		/* Wa_18018781329 */
 		wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
 		wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
 
-		/* Wa_14015795083 */
-		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+		if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+		    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+			/* Wa_14014830051 */
+			wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
+
+			/* Wa_14015795083 */
+			wa_write_clr(wal, GEN7_MISCCPCTL,
+				     GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+		}
 	}
 
 	/*
@@ -1718,7 +1723,8 @@  xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 static void
 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) {
+	/* Wa_14018778641: MTL */
+	if (IS_METEORLAKE(gt->i915)) {
 		/*
 		 * Wa_18018781329
 		 *