diff mbox series

[v2,1/7] drm/i915: Define bitmasks for ilk pfit window pos/size

Message ID 20230426135019.7603-2-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Scaler/pfit stuff | expand

Commit Message

Ville Syrjälä April 26, 2023, 1:50 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Define and use the bitmasks for the x/y components
of the ilk+ panel filter window pos/size registers.

Note that we stick to the full 16 bit mask even though
the actual hardware limits are lower (and somewhat
platform dependent). BDW is actually limited to
13 bits horizontal and 12 bits vertical, with the high
bits being hardwired to zero. HSW should have the same
limits as BDW. And pre-HSW should be limited to 12bits
in both directions as that's already the limit of the
transcoder timing registers. Curiously on HSW and earlier
platforms all 16 bits can actually be set, but presumably
the hardware ignores the high bits.

v2: Switch back to full 16bit masks since that's what
    we use transcoder timign regs and PIPESRC as well

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  8 ++++++++
 2 files changed, 16 insertions(+), 4 deletions(-)

Comments

Jani Nikula May 3, 2023, 8:21 a.m. UTC | #1 
On Wed, 26 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define and use the bitmasks for the x/y components
> of the ilk+ panel filter window pos/size registers.
>
> Note that we stick to the full 16 bit mask even though
> the actual hardware limits are lower (and somewhat
> platform dependent). BDW is actually limited to
> 13 bits horizontal and 12 bits vertical, with the high
> bits being hardwired to zero. HSW should have the same
> limits as BDW. And pre-HSW should be limited to 12bits
> in both directions as that's already the limit of the
> transcoder timing registers. Curiously on HSW and earlier
> platforms all 16 bits can actually be set, but presumably
> the hardware ignores the high bits.
>
> v2: Switch back to full 16bit masks since that's what
>     we use transcoder timign regs and PIPESRC as well
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
>  drivers/gpu/drm/i915/i915_reg.h              |  8 ++++++++
>  2 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bf391a6cd8d6..5e40a0ef3457 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -812,8 +812,10 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
>  	else
>  		intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
>  				  PF_FILTER_MED_3x3);
> -	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
> -	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
> +	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
> +			  PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
> +	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
> +			  PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
>  }
>  
>  static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> @@ -3246,8 +3248,10 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
>  	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
>  
>  	drm_rect_init(&crtc_state->pch_pfit.dst,
> -		      pos >> 16, pos & 0xffff,
> -		      size >> 16, size & 0xffff);
> +		      REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
> +		      REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
> +		      REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
> +		      REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
>  
>  	/*
>  	 * We currently do not free assignements of panel fitters on
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dde6e91055bd..f7294a9b5cfa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4025,8 +4025,16 @@
>  #define   PF_FILTER_EDGE_SOFTEN		REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
>  #define _PFA_WIN_SZ		0x68074
>  #define _PFB_WIN_SZ		0x68874
> +#define   PF_WIN_XSIZE_MASK	REG_GENMASK(31, 16)
> +#define   PF_WIN_XSIZE(w)	REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
> +#define   PF_WIN_YSIZE_MASK	REG_GENMASK(15, 0)
> +#define   PF_WIN_YSIZE(h)	REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
>  #define _PFA_WIN_POS		0x68070
>  #define _PFB_WIN_POS		0x68870
> +#define   PF_WIN_XPOS_MASK	REG_GENMASK(31, 16)
> +#define   PF_WIN_XPOS(x)	REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
> +#define   PF_WIN_YPOS_MASK	REG_GENMASK(15, 0)
> +#define   PF_WIN_YPOS(y)	REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
>  #define _PFA_VSCALE		0x68084
>  #define _PFB_VSCALE		0x68884
>  #define _PFA_HSCALE		0x68090
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf391a6cd8d6..5e40a0ef3457 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -812,8 +812,10 @@  static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 	else
 		intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 				  PF_FILTER_MED_3x3);
-	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
-	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
+	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
+			  PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
+	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
+			  PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
 }
 
 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -3246,8 +3248,10 @@  static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
 	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
 
 	drm_rect_init(&crtc_state->pch_pfit.dst,
-		      pos >> 16, pos & 0xffff,
-		      size >> 16, size & 0xffff);
+		      REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
+		      REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
+		      REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
+		      REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
 
 	/*
 	 * We currently do not free assignements of panel fitters on
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dde6e91055bd..f7294a9b5cfa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4025,8 +4025,16 @@ 
 #define   PF_FILTER_EDGE_SOFTEN		REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
 #define _PFA_WIN_SZ		0x68074
 #define _PFB_WIN_SZ		0x68874
+#define   PF_WIN_XSIZE_MASK	REG_GENMASK(31, 16)
+#define   PF_WIN_XSIZE(w)	REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
+#define   PF_WIN_YSIZE_MASK	REG_GENMASK(15, 0)
+#define   PF_WIN_YSIZE(h)	REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
 #define _PFA_WIN_POS		0x68070
 #define _PFB_WIN_POS		0x68870
+#define   PF_WIN_XPOS_MASK	REG_GENMASK(31, 16)
+#define   PF_WIN_XPOS(x)	REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
+#define   PF_WIN_YPOS_MASK	REG_GENMASK(15, 0)
+#define   PF_WIN_YPOS(y)	REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
 #define _PFA_VSCALE		0x68084
 #define _PFB_VSCALE		0x68884
 #define _PFA_HSCALE		0x68090