@@ -102,6 +102,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
+bool intel_dp_is_connected(struct intel_dp *intel_dp);
bool intel_digital_port_connected(struct intel_encoder *encoder);
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
@@ -1074,6 +1074,11 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
{
struct intel_connector *intel_connector = intel_dp->attached_connector;
+ if (!intel_dp_is_connected(intel_dp)) {
+ lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
+ return;
+ }
+
if (intel_dp->hobl_active) {
lt_dbg(intel_dp, DP_PHY_DPRX,
"Link Training failed with HOBL active, not enabling it from now on\n");
Prevent downgrading the link training maximum lane count/rate if the sink is disconnected - and so the link training failure is expected. In such cases modeset failures due to the reduced max link params would be just confusing for user space (instead of which the correct thing it should act on is the sink disconnect signaled by a hotplug event, requiring a disabling modeset). Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +++++ 2 files changed, 6 insertions(+)