| Message ID | 20230427150016.1566833-3-vinod.govindapillai@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mtl: add support for pmdemand | expand |
On Thu, Apr 27, 2023 at 06:00:10PM +0300, Vinod Govindapillai wrote: > >From MTL onwwards, pcode locks the QGV point based on peak BW of > the intended QGV point passed by the driver. So the peak BW > calculation must match the value expected by the pcode. Update > the calculations as per the Bspec. > > Bspec: 64636 > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bw.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index ab405c48ca3a..25ae4e5834d3 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, > val2 = intel_uncore_read(&dev_priv->uncore, > MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); > dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); > - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); > + sp->dclk = (16667 * dclk + 500) / 1000; Don't hand roll rounding. > sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); > sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); > > -- > 2.34.1
On Thu, 2023-04-27 at 18:04 +0300, Ville Syrjälä wrote: > On Thu, Apr 27, 2023 at 06:00:10PM +0300, Vinod Govindapillai wrote: > > > From MTL onwwards, pcode locks the QGV point based on peak BW of > > the intended QGV point passed by the driver. So the peak BW > > calculation must match the value expected by the pcode. Update > > the calculations as per the Bspec. > > > > Bspec: 64636 > > > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bw.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > > index ab405c48ca3a..25ae4e5834d3 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, > > val2 = intel_uncore_read(&dev_priv->uncore, > > MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); > > dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); > > - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); > > + sp->dclk = (16667 * dclk + 500) / 1000; > > Don't hand roll rounding. Hi Ville, I did not understand what you meant by this. This is as per the Bspec 64636. I am assuming, probably this is what pcode expects to get it compared with its internal reference qclk peak Bw. I will clarify with Art. And there is another requirement to get rid of div_round_up() of these BW calculations. Will address them separately. BR Vinod > > > sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); > > sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); > > > > -- > > 2.34.1 >
On Fri, 28 Apr 2023, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote: > On Thu, 2023-04-27 at 18:04 +0300, Ville Syrjälä wrote: >> On Thu, Apr 27, 2023 at 06:00:10PM +0300, Vinod Govindapillai wrote: >> > > From MTL onwwards, pcode locks the QGV point based on peak BW of >> > the intended QGV point passed by the driver. So the peak BW >> > calculation must match the value expected by the pcode. Update >> > the calculations as per the Bspec. >> > >> > Bspec: 64636 >> > >> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> >> > --- >> > drivers/gpu/drm/i915/display/intel_bw.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c >> > index ab405c48ca3a..25ae4e5834d3 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_bw.c >> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c >> > @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, >> > val2 = intel_uncore_read(&dev_priv->uncore, >> > MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); >> > dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); >> > - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); >> > + sp->dclk = (16667 * dclk + 500) / 1000; >> >> Don't hand roll rounding. > > Hi Ville, > > I did not understand what you meant by this. > > This is as per the Bspec 64636. I am assuming, probably this is what pcode expects to get it > compared with its internal reference qclk peak Bw. I will clarify with Art. > > And there is another requirement to get rid of div_round_up() of these BW calculations. Will address > them separately. The point is, no matter whether you need to round up or down or nearest, you need to use the DIV_ROUND_* helpers for that, not duplicate the logic here. No matter what bspec says. BR, Jani. > > BR > Vinod >> >> > sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); >> > sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); >> > >> > -- >> > 2.34.1 >> >
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index ab405c48ca3a..25ae4e5834d3 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, val2 = intel_uncore_read(&dev_priv->uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); + sp->dclk = (16667 * dclk + 500) / 1000; sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
From MTL onwwards, pcode locks the QGV point based on peak BW of the intended QGV point passed by the driver. So the peak BW calculation must match the value expected by the pcode. Update the calculations as per the Bspec. Bspec: 64636 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)