From patchwork Fri Apr 28 09:54:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 13226211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A785C77B7F for ; Fri, 28 Apr 2023 10:00:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5307C10ECE6; Fri, 28 Apr 2023 10:00:10 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1625F10ECB9 for ; Fri, 28 Apr 2023 09:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682675996; x=1714211996; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wK6x76aYBUbyjCH+KdwmSEtUsYU9cNQjl1jNzFlsKF0=; b=FCU01MU1BUxdkbUTK9+ZeuSe0dXwbyaoK2flgCw+/ezdpvoc6bewbQ41 3+YFvuLwbZZKDOzkPif/XY6XcIUJH71WfSDe3CtUK5pymHnMxFF6PNdYR 98wB9B9AjZwMUAWCllCEukyhl1Tbvvzm4kcScULqEB/GemZlw1Uf672c5 mJDtaiUBJRvU74WQ7d4upQfRRIG5NqUHNSQdCscvrc1MEKseBBYiw53mH KN99G37EU3C/hhuoz7RhzFFTURO1XtV+rkLcyw1sC30Ba6F+6BQO46mL+ UINB2bnWJp786wCHoEDXuJv0BlTrONZY5uDs9BO+JsELll8LgyWesK+YN A==; X-IronPort-AV: E=McAfee;i="6600,9927,10693"; a="375698265" X-IronPort-AV: E=Sophos;i="5.99,234,1677571200"; d="scan'208";a="375698265" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2023 02:59:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10693"; a="725295775" X-IronPort-AV: E=Sophos;i="5.99,234,1677571200"; d="scan'208";a="725295775" Received: from sorvi2.fi.intel.com ([10.237.72.194]) by orsmga008.jf.intel.com with ESMTP; 28 Apr 2023 02:59:53 -0700 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Apr 2023 12:54:32 +0300 Message-Id: <20230428095433.4109054-13-mika.kahola@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230428095433.4109054-1-mika.kahola@intel.com> References: <20230428095433.4109054-1-mika.kahola@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 12/13] drm/i915/mtl: Pin assignment for TypeC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Unlike previous platforms that used PORT_TX_DFLEXDPSP for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1 from which the max_lanes has to be calculated. Bspec: 50235, 65380 Reviewed-by: Matt Atwood Signed-off-by: Anusha Srivatsa Signed-off-by: Jose Roberto de Souza Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index b192265a3d78..4fca711a58bc 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -16,6 +16,10 @@ #include "intel_mg_phy_regs.h" #include "intel_tc.h" +#define DP_PIN_ASSIGNMENT_C 0x3 +#define DP_PIN_ASSIGNMENT_D 0x4 +#define DP_PIN_ASSIGNMENT_E 0x5 + enum tc_port_mode { TC_PORT_DISCONNECTED, TC_PORT_TBT_ALT, @@ -281,6 +285,27 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx); } +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + intel_wakeref_t wakeref; + u32 pin_mask; + + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); + + switch (pin_mask) { + default: + MISSING_CASE(pin_mask); + fallthrough; + case DP_PIN_ASSIGNMENT_D: + return 2; + case DP_PIN_ASSIGNMENT_C: + case DP_PIN_ASSIGNMENT_E: + return 4; + } +} + int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -294,6 +319,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) assert_tc_cold_blocked(tc); + if (DISPLAY_VER(i915) >= 14) + return mtl_tc_port_get_pin_assignment_mask(dig_port); + lane_mask = 0; with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) lane_mask = intel_tc_port_get_lane_mask(dig_port);