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[v2,7/8] drm/i915/mtl/huc: Use the media gt for the HuC getparam

Message ID 20230428185810.4127234-8-daniele.ceraolospurio@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: HuC loading and authentication for MTL | expand

Commit Message

Daniele Ceraolo Spurio April 28, 2023, 6:58 p.m. UTC
On MTL, for obvious reasons, HuC is only available on the media tile.
We already disable SW support for HuC on the root gt due to the
absence of VCS engines, but we also need to update the getparam to point
to the HuC struct in the media GT.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/i915_getparam.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

John Harrison May 25, 2023, 7:53 p.m. UTC | #1
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
> On MTL, for obvious reasons, HuC is only available on the media tile.
> We already disable SW support for HuC on the root gt due to the
> absence of VCS engines, but we also need to update the getparam to point
> to the HuC struct in the media GT.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> ---
>   drivers/gpu/drm/i915/i915_getparam.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 2238e096c957..7aa47550e4f2 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -98,7 +98,11 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
>   		value = sseu->min_eu_in_pool;
>   		break;
>   	case I915_PARAM_HUC_STATUS:
> -		value = intel_huc_check_status(&to_gt(i915)->uc.huc);
> +		/* On platform with a media GT, the HuC is on that GT */
> +		if (i915->media_gt)
> +			value = intel_huc_check_status(&i915->media_gt->uc.huc);
> +		else
> +			value = intel_huc_check_status(&to_gt(i915)->uc.huc);
I assume the intention is to ignore multi-tile complications? As in, all 
tiles are guaranteed to be the same so there is no point looking beyond 
the root tile?

Reviewed-by: John Harrison <John.C.Harrison@Intel.com>


>   		if (value < 0)
>   			return value;
>   		break;
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Patch

diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 2238e096c957..7aa47550e4f2 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -98,7 +98,11 @@  int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = sseu->min_eu_in_pool;
 		break;
 	case I915_PARAM_HUC_STATUS:
-		value = intel_huc_check_status(&to_gt(i915)->uc.huc);
+		/* On platform with a media GT, the HuC is on that GT */
+		if (i915->media_gt)
+			value = intel_huc_check_status(&i915->media_gt->uc.huc);
+		else
+			value = intel_huc_check_status(&to_gt(i915)->uc.huc);
 		if (value < 0)
 			return value;
 		break;