From patchwork Mon May 8 12:47:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13234500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24A16C77B73 for ; Mon, 8 May 2023 12:52:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B33810E289; Mon, 8 May 2023 12:52:05 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E24710E287 for ; Mon, 8 May 2023 12:52:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683550323; x=1715086323; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O8tPXy2tfQgrW+OJMwmm34SzHzn3kiXDJb8Pp8HbnHc=; b=X9TOyoI8O6PNx6xUgXSHvIGhO22KkYR9VC7/ySe1qflXExSEQAylMuOO fep+OxxUeLzFdIkgjkpILBqjWstx1cNSF2p9N/qsH6zWGmOuonRIav7vH u6+t8Z0TqpNqe5ZHSNdbXq3BCsKcDBkdYoauB0APYEcVtKufA8dIzMsZ7 qYGL5APZ7i8C/mt5+zMb9RJnw8S0vSv7fxAo5MWb5Ap6OnbGCb9w6Rwdi 60lkU653ekv32wVd5uAT3ZYLll+e5ndU63XNjeQxenMjC2ZqkHRi6n0FN 5fDQQmrpyyI0eFf7qzmeO6oGrl/O9XYHDRzA6jpjLRG20PV46WxRuHVs9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329994815" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="329994815" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:52:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="842675337" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="842675337" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:52:00 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2023 18:17:13 +0530 Message-Id: <20230508124715.2242478-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> References: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we use the highest input BPC supported by DP sink while using DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same input BPC that is used between Source and the PCON without DSC, which might not work even with the maximum FRL rate supported by HDMI2.1 sink. This patch calculates the max BPC that can be sufficient with either RGB or YCBCR420 format for the maximum FRL rate supported. v2: Rebase v3: Use the sink_format in the functions instead of ycbcr420 flag. v4: Rebase Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 60 ++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 24de25551a49..cc126a1a08b5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) return dig_port->base.type == INTEL_OUTPUT_EDP; } +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); static void intel_dp_unset_edid(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ @@ -1645,6 +1646,39 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } +static int +intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int max_bpc) +{ + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int req_rate_gbps; + int max_frl_rate = connector->display_info.hdmi.max_lanes * + connector->display_info.hdmi.max_frl_rate_per_lane; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (dsc_bpc[i] > max_bpc) + continue; + + req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000); + + /* YCBCR420 reduces data rate by 2 */ + if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + req_rate_gbps /= 2; + + if (req_rate_gbps < max_frl_rate) + return dsc_bpc[i] * 3; + } + + return 0; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1653,6 +1687,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, bool compute_pipe_bpp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; @@ -1668,10 +1704,30 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; - if (compute_pipe_bpp) + /* + * In cases where PCON with HDMI2.1 as branch device, if PCON supports + * DSC but HDMI2.1 sink does not supports DSC, there can be issues due + * to the bpc used. + * With DSC, a source-PCON pair can support the mode with higher bpcs. + * But PCON->Sink pair, cannot support the same bpc without sink having + * DSC support. + * So use the max BPC as input BPC that will be sufficient to show the + * mode without DSC from PCON->HDMI2.1 + */ + if (intel_dp_is_hdmi_2_1_sink(intel_dp) && + !connector->display_info.hdmi.dsc_cap.v_1p2) { + pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config, + conn_state->max_requested_bpc); + if (!pipe_bpp) { + drm_dbg_kms(&dev_priv->drm, + "No BPC possible to support the mode without HDMI2.1 DSC\n"); + return -EINVAL; + } + } else if (compute_pipe_bpp) { pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - else + } else { pipe_bpp = pipe_config->pipe_bpp; + } if (intel_dp->force_dsc_bpc) { pipe_bpp = intel_dp->force_dsc_bpc * 3;