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[v3,2/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

Message ID 20230515222423.224407-2-radhakrishna.sripada@intel.com (mailing list archive)
State New, archived
Headers show
Series [v3,1/2] drm/i915/mtl: Add MTL performance tuning changes | expand

Commit Message

Sripada, Radhakrishna May 15, 2023, 10:24 p.m. UTC
The dg2 workaround which requires the register for
DRAW_WATERMARK to be saved/restored during context reset/switch
is required on MTL-A step as well.

v2: Limit the WA for A-step
v3: Update the commit message.

Bspec: 68331
Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Matt Roper May 15, 2023, 10:47 p.m. UTC | #1
On Mon, May 15, 2023 at 03:24:23PM -0700, Radhakrishna Sripada wrote:
> The dg2 workaround which requires the register for
> DRAW_WATERMARK to be saved/restored during context reset/switch
> is required on MTL-A step as well.

Maybe it would be more clear if this was written as

        Like DG2, MTL a-step hardware is subject to Wa_16014892111 which
        requires that the any changes made to the DRAW_WATERMARK
        register be done via an INDIRECT_CTX batch buffer rather than
        through a regular context workaround.

        The bspec gives the same non-default recommended tuning value
        for DRAW_WATERMARK as DG2, so we can re-use the the INDIRECT_CTX
        code to apply that tuning setting on A-step hardware.

        Application of the tuning setting on B-step and later does not
        need INDIRECT_CTX handling and is already done in
        mtl_ctx_workarounds_init() as usual.

> 
> v2: Limit the WA for A-step
> v3: Update the commit message.
> 
> Bspec: 68331
> Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 81a96c52a92b..9c1007c44298 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1370,7 +1370,9 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>  					      cs, GEN12_GFX_CCS_AUX_NV);
>  
>  	/* Wa_16014892111 */
> -	if (IS_DG2(ce->engine->i915))
> +	if (IS_DG2(ce->engine->i915) ||
> +	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> +	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0))

As with the previous patch, it would be best to put the newest platform
first in the 'if' statement.  Aside from that (and the commit message
clarification above),

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

>  		cs = dg2_emit_draw_watermark_setting(cs);
>  
>  	return cs;
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 81a96c52a92b..9c1007c44298 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1370,7 +1370,9 @@  gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 					      cs, GEN12_GFX_CCS_AUX_NV);
 
 	/* Wa_16014892111 */
-	if (IS_DG2(ce->engine->i915))
+	if (IS_DG2(ce->engine->i915) ||
+	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
+	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0))
 		cs = dg2_emit_draw_watermark_setting(cs);
 
 	return cs;