| Message ID | 20230517004046.264131-1-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4,1/2] drm/i915/mtl: Add MTL performance tuning changes | expand |
Quoting Radhakrishna Sripada (2023-05-16 21:40:45-03:00) >MTL reuses the tuning parameters for DG2. Extend the dg2 >performance tuning parameters to MTL. > >v2: Add DRAW_WATERMARK tuning parameter. >v3: Limit DRAW_WATERMARK tuning to non A0 step. >v4: Reorder platform checks. > Restrict Blend fill caching optimization to Render GT. > >Bspec: 68331 >Cc: Haridhar Kalvala <haridhar.kalvala@intel.com> >Cc: Matt Roper <matthew.d.roper@intel.com> >Cc: Gustavo Sousa <gustavo.sousa@intel.com> >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> >--- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >index 786349e95487..b6d3185cf868 100644 >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >@@ -817,6 +817,12 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, > { > struct drm_i915_private *i915 = engine->i915; > >+ dg2_ctx_gt_tuning_init(engine, wal); >+ >+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || >+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) >+ wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); >+ I would put those (dg2_ctx_gt_tuning_init() call and DRAW_WATERMARK programming) in a separate mtl_ctx_gt_tuning_init() function. That would be more consistent with having tuning for context save/restore registers in separate functions and makes it easy to see this particular programming of DRAW_WATERMARK is a recommended tuning instead of a workaround. With that, Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> -- Gustavo Sousa > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { > /* Wa_14014947963 */ >@@ -1748,6 +1754,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > */ > static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) > { >+ if (IS_METEORLAKE(gt->i915)) { >+ if (gt->type != GT_MEDIA) >+ wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); >+ >+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); >+ } >+ > if (IS_PONTEVECCHIO(gt->i915)) { > wa_mcr_write(wal, XEHPC_L3SCRUB, > SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); >@@ -2944,7 +2957,7 @@ static void > add_render_compute_tuning_settings(struct drm_i915_private *i915, > struct i915_wa_list *wal) > { >- if (IS_DG2(i915)) >+ if (IS_METEORLAKE(i915) || IS_DG2(i915)) > wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); > > /* >-- >2.34.1 >
Thank you for the reviews. Pushed the patches. - Radhakrishna Sripada > -----Original Message----- > From: Sousa, Gustavo <gustavo.sousa@intel.com> > Sent: Wednesday, May 17, 2023 12:27 PM > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Sripada, Radhakrishna > <radhakrishna.sripada@intel.com>; Kalvala, Haridhar > <haridhar.kalvala@intel.com>; Roper, Matthew D > <matthew.d.roper@intel.com> > Subject: Re: [PATCH v4 1/2] drm/i915/mtl: Add MTL performance tuning > changes > > Quoting Radhakrishna Sripada (2023-05-16 21:40:45-03:00) > >MTL reuses the tuning parameters for DG2. Extend the dg2 > >performance tuning parameters to MTL. > > > >v2: Add DRAW_WATERMARK tuning parameter. > >v3: Limit DRAW_WATERMARK tuning to non A0 step. > >v4: Reorder platform checks. > > Restrict Blend fill caching optimization to Render GT. > > > >Bspec: 68331 > >Cc: Haridhar Kalvala <haridhar.kalvala@intel.com> > >Cc: Matt Roper <matthew.d.roper@intel.com> > >Cc: Gustavo Sousa <gustavo.sousa@intel.com> > >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > >--- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 15 ++++++++++++++- > > 1 file changed, 14 insertions(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > >index 786349e95487..b6d3185cf868 100644 > >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > >@@ -817,6 +817,12 @@ static void mtl_ctx_workarounds_init(struct > intel_engine_cs *engine, > > { > > struct drm_i915_private *i915 = engine->i915; > > > >+ dg2_ctx_gt_tuning_init(engine, wal); > >+ > >+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || > >+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) > >+ wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); > >+ > > I would put those (dg2_ctx_gt_tuning_init() call and DRAW_WATERMARK > programming) in a separate mtl_ctx_gt_tuning_init() function. That would > be more consistent with having tuning for context save/restore registers > in separate functions and makes it easy to see this particular programming of > DRAW_WATERMARK is a recommended tuning instead of a workaround. > > With that, > > Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> > > -- > Gustavo Sousa > > > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { > > /* Wa_14014947963 */ > >@@ -1748,6 +1754,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, > struct i915_wa_list *wal) > > */ > > static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) > > { > >+ if (IS_METEORLAKE(gt->i915)) { > >+ if (gt->type != GT_MEDIA) > >+ wa_mcr_write_or(wal, XEHP_L3SCQREG7, > BLEND_FILL_CACHING_OPT_DIS); > >+ > >+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); > >+ } > >+ > > if (IS_PONTEVECCHIO(gt->i915)) { > > wa_mcr_write(wal, XEHPC_L3SCRUB, > > SCRUB_CL_DWNGRADE_SHARED | > SCRUB_RATE_4B_PER_CLK); > >@@ -2944,7 +2957,7 @@ static void > > add_render_compute_tuning_settings(struct drm_i915_private *i915, > > struct i915_wa_list *wal) > > { > >- if (IS_DG2(i915)) > >+ if (IS_METEORLAKE(i915) || IS_DG2(i915)) > > wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, > STACKID_CTRL_512); > > > > /* > >-- > >2.34.1 > >
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 786349e95487..b6d3185cf868 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -817,6 +817,12 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, { struct drm_i915_private *i915 = engine->i915; + dg2_ctx_gt_tuning_init(engine, wal); + + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) + wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { /* Wa_14014947963 */ @@ -1748,6 +1754,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) */ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) { + if (IS_METEORLAKE(gt->i915)) { + if (gt->type != GT_MEDIA) + wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); + + wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); + } + if (IS_PONTEVECCHIO(gt->i915)) { wa_mcr_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); @@ -2944,7 +2957,7 @@ static void add_render_compute_tuning_settings(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_DG2(i915)) + if (IS_METEORLAKE(i915) || IS_DG2(i915)) wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); /*
MTL reuses the tuning parameters for DG2. Extend the dg2 performance tuning parameters to MTL. v2: Add DRAW_WATERMARK tuning parameter. v3: Limit DRAW_WATERMARK tuning to non A0 step. v4: Reorder platform checks. Restrict Blend fill caching optimization to Render GT. Bspec: 68331 Cc: Haridhar Kalvala <haridhar.kalvala@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)