From patchwork Wed May 17 00:40:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13244038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 419BAC77B7A for ; Wed, 17 May 2023 00:42:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97C1D10E12C; Wed, 17 May 2023 00:42:08 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFB9910E12C for ; Wed, 17 May 2023 00:42:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684284126; x=1715820126; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=M6i+w9zJQWqQEjriMyFjXfu6BviyFtNFctoHIKYr7sA=; b=bS0ZhPAF/5U1/Bjx1JhyBKYN56siOGywpf6mElVwcL2DLRkJS7BfGmWx wnM/Mcnb9bILlDblhSc8t4RVD5VZHeCvFvAHMIZvKcrIVpDPU3JMgoGbC BGRFDE8apIQLv1jRoBiKur2RHCZmP9VHFxgv2iwLZBSGmW7zi4XpcMVTO u46rf2dHLiM4C6C5k5rb8WGbboeycxFoASIqLHevktM8r9iaYn0o/yWL+ 3wyJEZdcLfDv/FglJf/3mrKITA09TWvcVSU1nH15Ot9sYNjBrfS87r9ha NvN56F7EuE1cHcrRBXEkab6+U1f2Z4ZHFqeXavLVFfGehkkHnN3QG+Q+S Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10712"; a="336177972" X-IronPort-AV: E=Sophos;i="5.99,280,1677571200"; d="scan'208";a="336177972" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2023 17:42:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10712"; a="813652876" X-IronPort-AV: E=Sophos;i="5.99,280,1677571200"; d="scan'208";a="813652876" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2023 17:42:04 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Tue, 16 May 2023 17:40:45 -0700 Message-Id: <20230517004046.264131-1-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/mtl: Add MTL performance tuning changes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matt Roper Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" MTL reuses the tuning parameters for DG2. Extend the dg2 performance tuning parameters to MTL. v2: Add DRAW_WATERMARK tuning parameter. v3: Limit DRAW_WATERMARK tuning to non A0 step. v4: Reorder platform checks. Restrict Blend fill caching optimization to Render GT. Bspec: 68331 Cc: Haridhar Kalvala Cc: Matt Roper Cc: Gustavo Sousa Signed-off-by: Radhakrishna Sripada Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 786349e95487..b6d3185cf868 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -817,6 +817,12 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, { struct drm_i915_private *i915 = engine->i915; + dg2_ctx_gt_tuning_init(engine, wal); + + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) + wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { /* Wa_14014947963 */ @@ -1748,6 +1754,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) */ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) { + if (IS_METEORLAKE(gt->i915)) { + if (gt->type != GT_MEDIA) + wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); + + wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); + } + if (IS_PONTEVECCHIO(gt->i915)) { wa_mcr_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); @@ -2944,7 +2957,7 @@ static void add_render_compute_tuning_settings(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_DG2(i915)) + if (IS_METEORLAKE(i915) || IS_DG2(i915)) wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); /*