| Message ID | 20230517194040.3857137-2-andrzej.hajda@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL | expand |
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index ebb2373dd73640..e80685ac92dbef 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -124,6 +124,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) pg_enable = GEN9_MEDIA_PG_ENABLE | GEN11_MEDIA_SAMPLER_PG_ENABLE; + /* Testing */ + else if (IS_ALDERLAKE_S(gt->i915) || IS_ALDERLAKE_P(gt->i915)) + pg_enable = 0; else pg_enable = GEN9_RENDER_PG_ENABLE |
Multiple CI tests fails with forcewake timeouts. Disabling power gating for render and media solves the issue. References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++ 1 file changed, 3 insertions(+)