From patchwork Mon May 22 23:07:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13251211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63305C7EE29 for ; Mon, 22 May 2023 23:08:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E146A10E2F3; Mon, 22 May 2023 23:08:25 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id D483C10E2F3 for ; Mon, 22 May 2023 23:08:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684796903; x=1716332903; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pnZHGPYhag4g3K2tEmtMFuY+T7i8hD1n5jVdtL1NK9w=; b=lXSuCta3RppakFh1ys0WNKUZE2k80s9jSN+nkpB+W+ZPYHAOTtSzYn+0 DsW0SJeAsB+3a17lUrBTf5YyilSekxcYTVZh5xmlVOCamGwADiuzDbHAS OTh6434AVmTHsjwWxDMAcDMqicgZt3MB1JwH+ZI/cgEaytrQFADrqiyp0 w7tmH7uUiNZffgQ7zJvMy3BFom/DC65IY7kMvyFjqH76LYZGCwxklhc+6 2OAOOaDZOOqHn8/DJYXVBLp3PLnNYCWQoWcbB/PZ9C+xuB8+9734d1GRB k/G4+uvohahPgaeSSi0aHgXEQ/+6we6crfkeIqF9XGhfnsOJpxFPWXl7y A==; X-IronPort-AV: E=McAfee;i="6600,9927,10718"; a="353093817" X-IronPort-AV: E=Sophos;i="6.00,184,1681196400"; d="scan'208,223";a="353093817" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2023 16:08:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10718"; a="773542623" X-IronPort-AV: E=Sophos;i="6.00,184,1681196400"; d="scan'208,223";a="773542623" Received: from cavram-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.251.220.199]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2023 16:08:20 -0700 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org Date: Tue, 23 May 2023 02:07:54 +0300 Message-Id: <20230522230759.153112-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230522230759.153112-1-vinod.govindapillai@intel.com> References: <20230522230759.153112-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v6 2/7] drm/i915: update the QGV point frequency calculations X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From MTL onwwards, pcode locks the QGV point based on peak BW of the intended QGV point passed by the driver. So the peak BW calculation must match the value expected by the pcode. Update the calculations as per the Bspec. v2: use DIV_ROUND_* macro for the calculations (Ville) Bspec: 64636 Signed-off-by: Vinod Govindapillai Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index ab405c48ca3a..c8075a37c3ab 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, val2 = intel_uncore_read(&dev_priv->uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); + sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk + 500, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);