From patchwork Wed May 24 23:03:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13254606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8A3BC77B7C for ; Wed, 24 May 2023 23:04:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56E9810E69F; Wed, 24 May 2023 23:04:10 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 26C9810E69F for ; Wed, 24 May 2023 23:04:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684969448; x=1716505448; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyfATA09M4kDbLsYonI0B8aDA1XKZzvWiKBrlGzM7qc=; b=b3XWmWKbZshQl3lXZIfdcB8dxYmNCZ/5eoKFZHX59Iuc2mg/BwLAS0zg EmY8AmPMWkeZolS87FlyGRKZdbz4zmXj4ztrJ+/RNfg4tyk4VFlv6X2DB QDgdS7HaQPrrhGT+9K28JaP4eEiV1OCUpFdRQvtpBOr8Y1UxOJNr85ELT /8Iu6gfnHykVjY/3rQk5Gt9AthYC0v45gCy7it0/w0HHOxjdKivxhlafQ 9gc3zfBg9w4129ZwnbTO4nSqhHumeCvYxdULVO+NmTUEHs0+VhXY1AQJ/ mQM0R4MJ4i6xMZ5ic/jREX0k8VVgQJ0UoGivuXAn6f3sDSGPqb5aTMwGv Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10720"; a="338289506" X-IronPort-AV: E=Sophos;i="6.00,190,1681196400"; d="scan'208,223";a="338289506" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2023 16:04:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10720"; a="951218413" X-IronPort-AV: E=Sophos;i="6.00,190,1681196400"; d="scan'208,223";a="951218413" Received: from peteratz-mobl.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.252.55.65]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2023 16:04:05 -0700 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org Date: Thu, 25 May 2023 02:03:37 +0300 Message-Id: <20230524230342.411273-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230524230342.411273-1-vinod.govindapillai@intel.com> References: <20230524230342.411273-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v8 2/7] drm/i915: update the QGV point frequency calculations X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From MTL onwwards, pcode locks the QGV point based on peak BW of the intended QGV point passed by the driver. So the peak BW calculation must match the value expected by the pcode. Update the calculations as per the Bspec. v2: use DIV_ROUND_* macro for the calculations (Ville) v3: Use only DIV_ROUN_CLOSEST and remove divisor / 2 again Bspec: 64636 Signed-off-by: Vinod Govindapillai Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index ab405c48ca3a..61b3babf2d83 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, val2 = intel_uncore_read(&dev_priv->uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); + sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);