From patchwork Tue Jun 6 06:43:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13268320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24C23C77B7A for ; Tue, 6 Jun 2023 06:43:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D50B610E22B; Tue, 6 Jun 2023 06:43:49 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id B699110E22B for ; Tue, 6 Jun 2023 06:43:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686033828; x=1717569828; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyfATA09M4kDbLsYonI0B8aDA1XKZzvWiKBrlGzM7qc=; b=l43Qe2iZiyhf3K1d6iDpAr3lJ6o0t157W4cWPOreIDDsjs9/yZfCZ64L N002qUm9Y0TEoClP5hHe6mMHB8Ay6XVoCe8kDN99XALuC5jkeZbaoYKun VUSSnm1FB4K1UlngkIo/AHjVK89p9/65oOIZI+PEn022b+Ke3KaVTKDFw kLw7qoG4hmfsaOm6c0Xn5vLOS5HGL/Aafytl2TuJVW34DUcIJ3GdDX3rd Fy/DkuGOgbXhdUkaf02ec8XyVjFFRLM91ob/j6yC3Vtk+IUgFoflLZXD6 bxQ1FdYv57apn8I0u9vLQ64TiGQA0B+/+7gxvKkOLFmy9dAJi2ld0KpH/ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="336940580" X-IronPort-AV: E=Sophos;i="6.00,219,1681196400"; d="scan'208,223";a="336940580" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 23:43:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="778865572" X-IronPort-AV: E=Sophos;i="6.00,219,1681196400"; d="scan'208,223";a="778865572" Received: from mgmohiud-mobl2.gar.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.249.42.181]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2023 23:43:46 -0700 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Jun 2023 09:43:22 +0300 Message-Id: <20230606064327.188226-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230606064327.188226-1-vinod.govindapillai@intel.com> References: <20230606064327.188226-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v13 2/7] drm/i915: update the QGV point frequency calculations X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From MTL onwwards, pcode locks the QGV point based on peak BW of the intended QGV point passed by the driver. So the peak BW calculation must match the value expected by the pcode. Update the calculations as per the Bspec. v2: use DIV_ROUND_* macro for the calculations (Ville) v3: Use only DIV_ROUN_CLOSEST and remove divisor / 2 again Bspec: 64636 Signed-off-by: Vinod Govindapillai Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index ab405c48ca3a..61b3babf2d83 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, val2 = intel_uncore_read(&dev_priv->uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); - sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); + sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);