| Message ID | 20230606191504.18099-16-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Load LUTs with DSB | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Wednesday, June 7, 2023 12:45 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 15/19] drm/i915: Introduce > skl_watermark_max_latency() > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The DSB code will want to know the maximum PkgC latency it has to contend > with. Add a helper to expose that information. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 14 ++++++++++++++ > drivers/gpu/drm/i915/display/skl_watermark.h | 2 ++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c > b/drivers/gpu/drm/i915/display/skl_watermark.c > index d1245c847f1c..a31adbca9dbc 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -3719,3 +3719,17 @@ void skl_watermark_debugfs_register(struct > drm_i915_private *i915) > debugfs_create_file("i915_sagv_status", 0444, minor- > >debugfs_root, i915, > &intel_sagv_status_fops); > } > + > +unsigned int skl_watermark_max_latency(struct drm_i915_private *i915) { > + int level; > + > + for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { > + unsigned int latency = skl_wm_latency(i915, level, NULL); > + > + if (latency) > + return latency; > + } > + > + return 0; > +} > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h > b/drivers/gpu/drm/i915/display/skl_watermark.h > index f91a3d4ddc07..edb61e33df83 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.h > +++ b/drivers/gpu/drm/i915/display/skl_watermark.h > @@ -46,6 +46,8 @@ void skl_watermark_ipc_update(struct drm_i915_private > *i915); bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); void > skl_watermark_debugfs_register(struct drm_i915_private *i915); > > +unsigned int skl_watermark_max_latency(struct drm_i915_private *i915); > + > void skl_wm_init(struct drm_i915_private *i915); > > struct intel_dbuf_state { > -- > 2.39.3
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index d1245c847f1c..a31adbca9dbc 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3719,3 +3719,17 @@ void skl_watermark_debugfs_register(struct drm_i915_private *i915) debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, i915, &intel_sagv_status_fops); } + +unsigned int skl_watermark_max_latency(struct drm_i915_private *i915) +{ + int level; + + for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { + unsigned int latency = skl_wm_latency(i915, level, NULL); + + if (latency) + return latency; + } + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index f91a3d4ddc07..edb61e33df83 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -46,6 +46,8 @@ void skl_watermark_ipc_update(struct drm_i915_private *i915); bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); void skl_watermark_debugfs_register(struct drm_i915_private *i915); +unsigned int skl_watermark_max_latency(struct drm_i915_private *i915); + void skl_wm_init(struct drm_i915_private *i915); struct intel_dbuf_state {