From patchwork Thu Jun 15 05:00:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bhadane, Dnyaneshwar" X-Patchwork-Id: 13280718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5040EB64DB for ; Thu, 15 Jun 2023 05:00:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1AEF110E17B; Thu, 15 Jun 2023 05:00:47 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 102B310E48A for ; Thu, 15 Jun 2023 05:00:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686805243; x=1718341243; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hcb0O4ENiJNXncpiRN/0wT1UHH4EHp1NO5xcDcXoN6k=; b=QQNPdIrsLFqTMjIaGGIH2pD2tEENXVFfIH1yQ3mmopIUz/aqqrEXZGGG 4OQKHuyoVXN7eAZppuNNBkpIM4630HiKHHFXmia7zi0Ssg+84socW21U5 g8yqJ18Qf7+hk7sQh2qoSZS2Zx99+yQfr3qUMYSz7qeratAoKrIPHxHiv xR7udS8enjMW7Tofq4yNe7DNASASfFxqIY9gU9ZQ+vgY65nfP+aoDAoYB xEoxTe49x/B0zAaqUT3bNGACAn8bTOeN9qVls0ERkhWyzipY1qKzzKKi0 7TDawP8543x8HOYWMafOymBaSGUe2ryX8NxlucxgkuzE8ZtEUIyp0kz1M g==; X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="361291153" X-IronPort-AV: E=Sophos;i="6.00,243,1681196400"; d="scan'208";a="361291153" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2023 22:00:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="689649535" X-IronPort-AV: E=Sophos;i="6.00,243,1681196400"; d="scan'208";a="689649535" Received: from pltuser2-ms-7d25.iind.intel.com ([10.190.239.58]) by orsmga006.jf.intel.com with ESMTP; 14 Jun 2023 22:00:41 -0700 From: Dnyaneshwar Bhadane To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Jun 2023 10:30:15 +0530 Message-Id: <20230615050015.3105902-12-dnyaneshwar.bhadane@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615050015.3105902-1-dnyaneshwar.bhadane@intel.com> References: <20230615050015.3105902-1-dnyaneshwar.bhadane@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/11] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dnyaneshwar.bhadane@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Follow consistent naming convention. Replace ADLP with ALDERLAKE_P Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 831d1258ea3f..d4d4bf72bc6d 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3562,7 +3562,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; - } else if (IS_ADLP_RPLU(dev_priv)) { + } else if (IS_ALDERLAKE_RPLU(dev_priv)) { dev_priv->display.cdclk.table = rplu_cdclk_table; dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; } else { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1dad0c9b4f30..c6ad78381dd1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -591,7 +591,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) #define IS_ALDERLAKE_P_RPLP(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) -#define IS_ADLP_RPLU(i915) \ +#define IS_ALDERLAKE_RPLU(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) #define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \ (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)