From patchwork Thu Jun 15 05:00:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bhadane, Dnyaneshwar" X-Patchwork-Id: 13280715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5AAC9EB64D9 for ; Thu, 15 Jun 2023 05:00:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B56D110E488; Thu, 15 Jun 2023 05:00:41 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 949E310E487 for ; Thu, 15 Jun 2023 05:00:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686805235; x=1718341235; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+MSqjLZ7+140KwTlkb0MPVrwqvra+n1PonQHl8PP77Y=; b=CIPULjXCkcVnA7HCtBxvYisAZKx2KsDR80BFm2LdmEgTaNcPXHqy5E5B KdnBxm39ErLF1ZS7Psxt6vQkxITaayZl9/eT7Ea4diqlAlBVErwIhKz0C NBICbNkPm3znwMusCqfLFlVUvZiQb3T5iuPCYRuRl7qzfPmtaWHMFIx9w CHfGIJb0iNf55ZFkxsLZTMDirJ1RzABZLAxWYU6k2z/Cm9Pb3cvZb/sje wH9jouMg2XnXiIMIgg8kRXlsdAzeOfYMxQ5Fx1bAy6w3MBuL/QUhknZVj oiwd4B9Ak2zf+m5O9uMLZbPcm7ZnP3Y8MiQTEUtTUSST3JHsXMAEp5sHA g==; X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="361291130" X-IronPort-AV: E=Sophos;i="6.00,243,1681196400"; d="scan'208";a="361291130" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2023 22:00:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="689649491" X-IronPort-AV: E=Sophos;i="6.00,243,1681196400"; d="scan'208";a="689649491" Received: from pltuser2-ms-7d25.iind.intel.com ([10.190.239.58]) by orsmga006.jf.intel.com with ESMTP; 14 Jun 2023 22:00:33 -0700 From: Dnyaneshwar Bhadane To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Jun 2023 10:30:11 +0530 Message-Id: <20230615050015.3105902-8-dnyaneshwar.bhadane@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615050015.3105902-1-dnyaneshwar.bhadane@intel.com> References: <20230615050015.3105902-1-dnyaneshwar.bhadane@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/11] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dnyaneshwar.bhadane@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Driver refers to the platfrom Alderlake P as ADLP in places and ALDERLAKE_P in some. Making the consistent change to avoid confusion of the right naming convention for the platform. Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++---- drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 2acfa0435675..831d1258ea3f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3559,7 +3559,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.cdclk.table = dg2_cdclk_table; } else if (IS_ALDERLAKE_P(dev_priv)) { /* Wa_22011320316:adl-p[a0] */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; } else if (IS_ADLP_RPLU(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c6d376d414b8..47fe8311067e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3781,7 +3781,7 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte { u32 val; - if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || + if (!IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0) || pll->info->id != DPLL_ID_ICL_DPLL0) return; /* diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f61d39d2b0fc..00c98c2b4324 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -639,7 +639,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) } /* Wa_22012278275:adl-p */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { static const u8 map[] = { 2, /* 5 lines */ 1, /* 6 lines */ @@ -807,7 +807,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, return; /* Wa_16011303918:adl-p */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) return; /* @@ -975,7 +975,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { + if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); return false; } @@ -1033,7 +1033,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, /* Wa_16011303918:adl-p */ if (crtc_state->vrr.enable && - IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { + IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, not compatible with HW stepping + VRR\n"); return false; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 25b06ced9ce7..2458a9ea25ba 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, return false; /* Wa_22011186057 */ - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) return false; if (DISPLAY_VER(i915) >= 11) @@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, return false; /* Wa_22011186057 */ - if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) + if (IS_ALDERLAKE_P_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) return false; /* Wa_14013215631 */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3c4a66f1a7ba..08e14cf225b5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -677,11 +677,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_ALDERLAKE_S(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until)) -#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ +#define IS_ALDERLAKE_P_DISPLAY_STEP(__i915, since, until) \ (IS_ALDERLAKE_P(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -#define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \ +#define IS_ALDERLAKE_P_GRAPHICS_STEP(__i915, since, until) \ (IS_ALDERLAKE_P(__i915) && \ IS_GRAPHICS_STEP(__i915, since, until))