diff mbox series

drm/i915/display: remove display raw reg read/write micro-optimizations

Message ID 20230621183805.251128-1-jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/display: remove display raw reg read/write micro-optimizations | expand

Commit Message

Jani Nikula June 21, 2023, 6:38 p.m. UTC
Convert the raw_reg_read() and raw_reg_write() calls in display GU MISC
and INT CTL handling to regular intel_uncore_read() and
intel_uncore_write(). These were neglible micro-optimizations, and
removing them helps the display code reuse in the Xe driver.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

Comments

Andi Shyti June 22, 2023, 2:08 p.m. UTC | #1
Hi Jani,

On Wed, Jun 21, 2023 at 09:38:05PM +0300, Jani Nikula wrote:
> Convert the raw_reg_read() and raw_reg_write() calls in display GU MISC
> and INT CTL handling to regular intel_uncore_read() and
> intel_uncore_write(). These were neglible micro-optimizations, and

/neglible/negligible/

> removing them helps the display code reuse in the Xe driver.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 

Andi
Jani Nikula June 27, 2023, 7:53 a.m. UTC | #2
On Thu, 22 Jun 2023, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> Hi Jani,
>
> On Wed, Jun 21, 2023 at 09:38:05PM +0300, Jani Nikula wrote:
>> Convert the raw_reg_read() and raw_reg_write() calls in display GU MISC
>> and INT CTL handling to regular intel_uncore_read() and
>> intel_uncore_write(). These were neglible micro-optimizations, and
>
> /neglible/negligible/
>
>> removing them helps the display code reuse in the Xe driver.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 

Thanks, but back to the drawing board:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119703v1/bat-dg2-9/igt@i915_pm_rpm@module-reload.html#dmesg-warnings1253

>
> Andi
Andi Shyti June 28, 2023, 5:17 p.m. UTC | #3
Hi Jani,

On Tue, Jun 27, 2023 at 10:53:01AM +0300, Jani Nikula wrote:
> On Thu, 22 Jun 2023, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> > Hi Jani,
> >
> > On Wed, Jun 21, 2023 at 09:38:05PM +0300, Jani Nikula wrote:
> >> Convert the raw_reg_read() and raw_reg_write() calls in display GU MISC
> >> and INT CTL handling to regular intel_uncore_read() and
> >> intel_uncore_write(). These were neglible micro-optimizations, and
> >
> > /neglible/negligible/
> >
> >> removing them helps the display code reuse in the Xe driver.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 
> 
> Thanks, but back to the drawing board:
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119703v1/bat-dg2-9/igt@i915_pm_rpm@module-reload.html#dmesg-warnings1253

Have you tried using intel_uncore_{read,write}_fw()?

Andi
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index ae98c99c5378..fda06f6c4a4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1149,15 +1149,14 @@  void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 
 u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
 {
-	void __iomem * const regs = i915->uncore.regs;
 	u32 iir;
 
 	if (!(master_ctl & GEN11_GU_MISC_IRQ))
 		return 0;
 
-	iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
+	iir = intel_uncore_read(&i915->uncore, GEN11_GU_MISC_IIR);
 	if (likely(iir))
-		raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
+		intel_uncore_write(&i915->uncore, GEN11_GU_MISC_IIR, iir);
 
 	return iir;
 }
@@ -1170,18 +1169,19 @@  void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
 
 void gen11_display_irq_handler(struct drm_i915_private *i915)
 {
-	void __iomem * const regs = i915->uncore.regs;
-	const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
+	u32 disp_ctl;
+
+	disp_ctl = intel_uncore_read(&i915->uncore, GEN11_DISPLAY_INT_CTL);
 
 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
 	/*
 	 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
 	 * for the display related bits.
 	 */
-	raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
+	intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL, 0x0);
 	gen8_de_irq_handler(i915, disp_ctl);
-	raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
-		      GEN11_DISPLAY_IRQ_ENABLE);
+	intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL,
+			   GEN11_DISPLAY_IRQ_ENABLE);
 
 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
 }