| Message ID | 20230627153451.2834196-2-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | HDMI 2.0/DP1p62Gbps skew violation when there is skew between DL PCLK | expand |
On Tue, Jun 27, 2023 at 09:04:51PM +0530, Mitul Golani wrote: > When doing type-C PHY voltage swing programming for HDMI and > DP 1.62Gbps, program DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable] > to '1'. For other DP frequencies, program > DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable] to '0'. > > This Workaround is specific to Display Version 13 > > Wa_15010727533 > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 2 files changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 61722556bb47..5a6f048f4f1c 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1362,6 +1362,19 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, > intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), > DKL_TX_DP20BITMODE, 0); > > + if (DISPLAY_VER(dev_priv) == 13) { The above check here is equivalent to IS_ALDERLAKE_P(), so the programming should be done under that condition below, along with the other bits in DKL_TX_DPCNTL2. Also the WA is limited to STEP_A0 .. STEP_C0. > + if ((crtc_state->port_clock == 594000 && > + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) || > + (crtc_state->port_clock == 162000 && > + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))) { > + intel_de_rmw(dev_priv, DKLP_TX_DPCNTL2(tc_port), > + LOADGEN_SHARING_PMD_DISABLE, 1); Must use intel_dkl_phy_rmw() with DKL regs. > + } else { > + intel_de_rmw(dev_priv, DKLP_TX_DPCNTL2(tc_port), > + LOADGEN_SHARING_PMD_DISABLE, 0); > + } > + } > + > if (IS_ALDERLAKE_P(dev_priv)) { > u32 val; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index dcf64e32cd54..5487301d4ad3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6663,4 +6663,10 @@ enum skl_power_gate { > > #define MTL_MEDIA_GSI_BASE 0x380000 > > +#define _DKLP_PCS_GLUE_TX_DPCNTL2 0xB68 These registers are defined in intel_dkl_phy_regs.h. Not sure about the above offset. There's been updates to the spec and I think the last known good value is 0x02c8 defined at Bspec 49295 That is just the already defined DKL_TX_DPCNTL2. > +#define LOADGEN_SHARING_PMD_DISABLE REG_BIT(2) This doesn't seem to match either bspec 55359, where bit 2 is cfg_dp20bitmode and bit 12 is loadgen_sharing_pmd_disable. > +#define DKLP_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ > + _DKL_PHY1_BASE, \ > + _DKL_PHY2_BASE) + \ > + _DKLP_PCS_GLUE_TX_DPCNTL2) > #endif /* _I915_REG_H_ */ > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 61722556bb47..5a6f048f4f1c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1362,6 +1362,19 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), DKL_TX_DP20BITMODE, 0); + if (DISPLAY_VER(dev_priv) == 13) { + if ((crtc_state->port_clock == 594000 && + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) || + (crtc_state->port_clock == 162000 && + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))) { + intel_de_rmw(dev_priv, DKLP_TX_DPCNTL2(tc_port), + LOADGEN_SHARING_PMD_DISABLE, 1); + } else { + intel_de_rmw(dev_priv, DKLP_TX_DPCNTL2(tc_port), + LOADGEN_SHARING_PMD_DISABLE, 0); + } + } + if (IS_ALDERLAKE_P(dev_priv)) { u32 val; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dcf64e32cd54..5487301d4ad3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6663,4 +6663,10 @@ enum skl_power_gate { #define MTL_MEDIA_GSI_BASE 0x380000 +#define _DKLP_PCS_GLUE_TX_DPCNTL2 0xB68 +#define LOADGEN_SHARING_PMD_DISABLE REG_BIT(2) +#define DKLP_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ + _DKL_PHY1_BASE, \ + _DKL_PHY2_BASE) + \ + _DKLP_PCS_GLUE_TX_DPCNTL2) #endif /* _I915_REG_H_ */
When doing type-C PHY voltage swing programming for HDMI and DP 1.62Gbps, program DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable] to '1'. For other DP frequencies, program DKLP_PCS_GLUE_TX_DPCNTL2[loadgen_sharing_pmd_disable] to '0'. This Workaround is specific to Display Version 13 Wa_15010727533 Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 2 files changed, 19 insertions(+)