From patchwork Tue Jul 4 10:31:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13300953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF533EB64DA for ; Tue, 4 Jul 2023 10:31:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80F0510E2CA; Tue, 4 Jul 2023 10:31:16 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3A6D10E2CA for ; Tue, 4 Jul 2023 10:31:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688466673; x=1720002673; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IfqZQ+mOP0V1nFC1a2Y5N9/iBsU69W/b/UQAYdZ3NoU=; b=XAIpa+ot9ApsYbS0YhPulhDRrv0t89fO3QMr16Srjw95ZljjD2nK/FNQ mzopJ+D3CCnivNGv1m7oB0/PjBkvBPDywA4Ym5AcAQt/lARfGeDN0McxN 4hFiAcAYdEaukrQbA5a5uGZ1lMAK9OtAEt7R7r9sroQr+K6q5Rvr2/C2Z oosf4pLX66VTS1Acp5jjAKAEFYFS7Krq5PRVXbzX+I/fP4sUBVp82e3zx BVRqSxR7GFkoQqGG5uu2QKKFySQHuarPtUuuBy1hG8Hc/f+00pOW9DPN9 EBfOMFzCYx+ZC9rT4UhsVB5Bnl0kTi2tzoMmw1IYFy/FwSdxCBdzvpkOP A==; X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="342680268" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="342680268" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2023 03:31:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="718870687" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="718870687" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by orsmga002.jf.intel.com with ESMTP; 04 Jul 2023 03:31:11 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Tue, 4 Jul 2023 13:31:07 +0300 Message-Id: <20230704103107.11237-3-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230704103107.11237-1-stanislav.lisovskiy@intel.com> References: <20230704103107.11237-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are currently having FIFO underruns happening for kms_dsc test case, problem is that, we check if curreny cdclk is >= pixel rate only if there is a single VDSC engine enabled(i.e dsc_split=false) however if we happen to have 2 VDSC engines enabled, we just kinda rely that this would be automatically enough. However pixel rate can be even >= than VDSC clock(cdclk) * 2, so in that case even with 2 VDSC engines enabled, we still need to tweak it up. So lets compare pixel rate with cdclk * slice count(VDSC engine count) and check if it still requires bumping up. Previously we had to bump up CDCLK many times for similar reasons. v2: - Use new intel_dsc_get_num_vdsc_instances to determine number of VDSC engines, instead of slice count(Ankit Nautiyal) Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4207863b7b2a..f04cebd01724 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -37,6 +37,7 @@ #include "intel_pci_config.h" #include "intel_pcode.h" #include "intel_psr.h" +#include "intel_vdsc.h" #include "vlv_sideband.h" /** @@ -2607,9 +2608,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * When we decide to use only one VDSC engine, since * each VDSC operates with 1 ppc throughput, pixel clock * cannot be higher than the VDSC clock (cdclk) + * If there 2 VDSC engines, then pixel clock can't be higher than + * VDSC clock(cdclk) * 2. However even that can still be not enough. + * Slice count reflects amount of VDSC engines, + * so lets use that to determine, if need still need to tweak CDCLK higher. */ - if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) - min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + if (crtc_state->dsc.compression_enable) { + u8 num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); + + min_cdclk = max_t(int, min_cdclk, + crtc_state->pixel_rate / num_vdsc_instances); + } /* * HACK. Currently for TGL/DG2 platforms we calculate