| Message ID | 20230705095518.3690951-1-tvrtko.ursulin@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Remove some dead "code" | expand |
On Wed, 05 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Commit 2caffbf11762 ("drm/i915: Revoke mmaps and prevent access to fence > registers across reset") removed the temporary implementation of a reset > under stop machine but forgot to remove this one commented out define. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_reset.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c > index 6916eba3bd33..cdbc08dad7ae 100644 > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > @@ -35,9 +35,6 @@ > > #define RESET_MAX_RETRIES 3 > > -/* XXX How to handle concurrent GGTT updates using tiling registers? */ > -#define RESET_UNDER_STOP_MACHINE 0 > - > static void client_mark_guilty(struct i915_gem_context *ctx, bool banned) > { > struct drm_i915_file_private *file_priv = ctx->file_priv;
On 05/07/2023 13:08, Jani Nikula wrote: > On Wed, 05 Jul 2023, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> Commit 2caffbf11762 ("drm/i915: Revoke mmaps and prevent access to fence >> registers across reset") removed the temporary implementation of a reset >> under stop machine but forgot to remove this one commented out define. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> Thanks, pushed! Regards, Tvrtko >> --- >> drivers/gpu/drm/i915/gt/intel_reset.c | 3 --- >> 1 file changed, 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c >> index 6916eba3bd33..cdbc08dad7ae 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_reset.c >> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c >> @@ -35,9 +35,6 @@ >> >> #define RESET_MAX_RETRIES 3 >> >> -/* XXX How to handle concurrent GGTT updates using tiling registers? */ >> -#define RESET_UNDER_STOP_MACHINE 0 >> - >> static void client_mark_guilty(struct i915_gem_context *ctx, bool banned) >> { >> struct drm_i915_file_private *file_priv = ctx->file_priv; >
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 6916eba3bd33..cdbc08dad7ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -35,9 +35,6 @@ #define RESET_MAX_RETRIES 3 -/* XXX How to handle concurrent GGTT updates using tiling registers? */ -#define RESET_UNDER_STOP_MACHINE 0 - static void client_mark_guilty(struct i915_gem_context *ctx, bool banned) { struct drm_i915_file_private *file_priv = ctx->file_priv;