| Message ID | 20230717173059.422892-4-andi.shyti@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update AUX invalidation sequence | expand |
Hi, On Mon, Jul 17, 2023 at 07:30:56PM +0200, Andi Shyti wrote: > In preparation of the next patch allign with the datasheet (BSPEC > 47112) with the naming of the pipe control set of flag values. > The variable "flags" in gen12_emit_flush_rcs() is applied as a > set of flags called Bit Group 1. > > Define also the Bit Group 0 as bit_group_0 where currently only > PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: <stable@vger.kernel.org> # v5.8+ > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +++++++++++++----------- > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index bee3b7dc595cf..3c935d6b68bf0 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -210,7 +210,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > mode |= EMIT_FLUSH; > > if (mode & EMIT_FLUSH) { > - u32 flags = 0; > + u32 bit_group_0 = 0; > + u32 bit_group_1 = 0; I could eventually add here a comment to explain better the meaning of these two bit_group_{0,1}. Andi
On Mon, Jul 17, 2023 at 07:30:56PM +0200, Andi Shyti wrote: > In preparation of the next patch allign with the datasheet (BSPEC s/allign/align/ Otherwise, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > 47112) with the naming of the pipe control set of flag values. > The variable "flags" in gen12_emit_flush_rcs() is applied as a > set of flags called Bit Group 1. > > Define also the Bit Group 0 as bit_group_0 where currently only > PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: <stable@vger.kernel.org> # v5.8+ > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +++++++++++++----------- > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index bee3b7dc595cf..3c935d6b68bf0 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -210,7 +210,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > mode |= EMIT_FLUSH; > > if (mode & EMIT_FLUSH) { > - u32 flags = 0; > + u32 bit_group_0 = 0; > + u32 bit_group_1 = 0; > int err; > u32 *cs; > > @@ -218,32 +219,33 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > if (err) > return err; > > - flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; > - flags |= PIPE_CONTROL_FLUSH_L3; > - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > + bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > + > + bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; > + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; > + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > + bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > /* Wa_1409600907:tgl,adl-p */ > - flags |= PIPE_CONTROL_DEPTH_STALL; > - flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; > - flags |= PIPE_CONTROL_FLUSH_ENABLE; > + bit_group_1 |= PIPE_CONTROL_DEPTH_STALL; > + bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE; > + bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE; > > - flags |= PIPE_CONTROL_STORE_DATA_INDEX; > - flags |= PIPE_CONTROL_QW_WRITE; > + bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX; > + bit_group_1 |= PIPE_CONTROL_QW_WRITE; > > - flags |= PIPE_CONTROL_CS_STALL; > + bit_group_1 |= PIPE_CONTROL_CS_STALL; > > if (!HAS_3D_PIPELINE(engine->i915)) > - flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > + bit_group_1 &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > else if (engine->class == COMPUTE_CLASS) > - flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > + bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > cs = intel_ring_begin(rq, 6); > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - cs = gen12_emit_pipe_control(cs, > - PIPE_CONTROL0_HDC_PIPELINE_FLUSH, > - flags, LRC_PPHWSP_SCRATCH_ADDR); > + cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1, > + LRC_PPHWSP_SCRATCH_ADDR); > intel_ring_advance(rq, cs); > } > > -- > 2.40.1 >
On 17.07.2023 19:30, Andi Shyti wrote: > In preparation of the next patch allign with the datasheet (BSPEC > 47112) with the naming of the pipe control set of flag values. > The variable "flags" in gen12_emit_flush_rcs() is applied as a > set of flags called Bit Group 1. > > Define also the Bit Group 0 as bit_group_0 where currently only > PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: <stable@vger.kernel.org> # v5.8+ > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +++++++++++++----------- > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index bee3b7dc595cf..3c935d6b68bf0 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -210,7 +210,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > mode |= EMIT_FLUSH; > > if (mode & EMIT_FLUSH) { > - u32 flags = 0; > + u32 bit_group_0 = 0; > + u32 bit_group_1 = 0; For me flags0 and flags1 seems more readable as in *gen8_emit_pipe_control(batch, flags0, flags1, offset), but no strong feelings, but if bit_group is chosen arguments of *gen8_emit_pipe_control could be changed as well. Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Regards Andrzej > int err; > u32 *cs; > > @@ -218,32 +219,33 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > if (err) > return err; > > - flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; > - flags |= PIPE_CONTROL_FLUSH_L3; > - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > + bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > + > + bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; > + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; > + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > + bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > /* Wa_1409600907:tgl,adl-p */ > - flags |= PIPE_CONTROL_DEPTH_STALL; > - flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; > - flags |= PIPE_CONTROL_FLUSH_ENABLE; > + bit_group_1 |= PIPE_CONTROL_DEPTH_STALL; > + bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE; > + bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE; > > - flags |= PIPE_CONTROL_STORE_DATA_INDEX; > - flags |= PIPE_CONTROL_QW_WRITE; > + bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX; > + bit_group_1 |= PIPE_CONTROL_QW_WRITE; > > - flags |= PIPE_CONTROL_CS_STALL; > + bit_group_1 |= PIPE_CONTROL_CS_STALL; > > if (!HAS_3D_PIPELINE(engine->i915)) > - flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > + bit_group_1 &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > else if (engine->class == COMPUTE_CLASS) > - flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > + bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > cs = intel_ring_begin(rq, 6); > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - cs = gen12_emit_pipe_control(cs, > - PIPE_CONTROL0_HDC_PIPELINE_FLUSH, > - flags, LRC_PPHWSP_SCRATCH_ADDR); > + cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1, > + LRC_PPHWSP_SCRATCH_ADDR); > intel_ring_advance(rq, cs); > } >
Thanks for cleaning this. With Matt's suggestion, this is Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> On 7/17/2023 7:30 PM, Andi Shyti wrote: > In preparation of the next patch allign with the datasheet (BSPEC > 47112) with the naming of the pipe control set of flag values. > The variable "flags" in gen12_emit_flush_rcs() is applied as a > set of flags called Bit Group 1. > > Define also the Bit Group 0 as bit_group_0 where currently only > PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: <stable@vger.kernel.org> # v5.8+ > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +++++++++++++----------- > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index bee3b7dc595cf..3c935d6b68bf0 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -210,7 +210,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > mode |= EMIT_FLUSH; > > if (mode & EMIT_FLUSH) { > - u32 flags = 0; > + u32 bit_group_0 = 0; > + u32 bit_group_1 = 0; > int err; > u32 *cs; > > @@ -218,32 +219,33 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > if (err) > return err; > > - flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; > - flags |= PIPE_CONTROL_FLUSH_L3; > - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > + bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > + > + bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; > + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; > + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > + bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > /* Wa_1409600907:tgl,adl-p */ > - flags |= PIPE_CONTROL_DEPTH_STALL; > - flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; > - flags |= PIPE_CONTROL_FLUSH_ENABLE; > + bit_group_1 |= PIPE_CONTROL_DEPTH_STALL; > + bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE; > + bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE; > > - flags |= PIPE_CONTROL_STORE_DATA_INDEX; > - flags |= PIPE_CONTROL_QW_WRITE; > + bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX; > + bit_group_1 |= PIPE_CONTROL_QW_WRITE; > > - flags |= PIPE_CONTROL_CS_STALL; > + bit_group_1 |= PIPE_CONTROL_CS_STALL; > > if (!HAS_3D_PIPELINE(engine->i915)) > - flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > + bit_group_1 &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > else if (engine->class == COMPUTE_CLASS) > - flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > + bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > cs = intel_ring_begin(rq, 6); > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - cs = gen12_emit_pipe_control(cs, > - PIPE_CONTROL0_HDC_PIPELINE_FLUSH, > - flags, LRC_PPHWSP_SCRATCH_ADDR); > + cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1, > + LRC_PPHWSP_SCRATCH_ADDR); > intel_ring_advance(rq, cs); > } >
Hi Andrzej, On Mon, Jul 17, 2023 at 08:21:40PM +0200, Andrzej Hajda wrote: > On 17.07.2023 19:30, Andi Shyti wrote: > > In preparation of the next patch allign with the datasheet (BSPEC > > 47112) with the naming of the pipe control set of flag values. > > The variable "flags" in gen12_emit_flush_rcs() is applied as a > > set of flags called Bit Group 1. > > > > Define also the Bit Group 0 as bit_group_0 where currently only > > PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. > > > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > > Cc: <stable@vger.kernel.org> # v5.8+ > > --- > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +++++++++++++----------- > > 1 file changed, 18 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > index bee3b7dc595cf..3c935d6b68bf0 100644 > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > @@ -210,7 +210,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > > mode |= EMIT_FLUSH; > > if (mode & EMIT_FLUSH) { > > - u32 flags = 0; > > + u32 bit_group_0 = 0; > > + u32 bit_group_1 = 0; > > For me flags0 and flags1 seems more readable as in > *gen8_emit_pipe_control(batch, flags0, flags1, offset), but no strong > feelings, but if bit_group is chosen arguments of *gen8_emit_pipe_control > could be changed as well. yes, I thought to update all of them, as well for consistency. I like the name bit_group_0/1 because it's similar to the datasheet. I had some confusion about it earlier and I think this can help to improve readability. Will update all the other functions, as well. > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Thanks! Andi
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index bee3b7dc595cf..3c935d6b68bf0 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -210,7 +210,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) mode |= EMIT_FLUSH; if (mode & EMIT_FLUSH) { - u32 flags = 0; + u32 bit_group_0 = 0; + u32 bit_group_1 = 0; int err; u32 *cs; @@ -218,32 +219,33 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) if (err) return err; - flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; - flags |= PIPE_CONTROL_FLUSH_L3; - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; + bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; + + bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; + bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; /* Wa_1409600907:tgl,adl-p */ - flags |= PIPE_CONTROL_DEPTH_STALL; - flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; - flags |= PIPE_CONTROL_FLUSH_ENABLE; + bit_group_1 |= PIPE_CONTROL_DEPTH_STALL; + bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE; + bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE; - flags |= PIPE_CONTROL_STORE_DATA_INDEX; - flags |= PIPE_CONTROL_QW_WRITE; + bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX; + bit_group_1 |= PIPE_CONTROL_QW_WRITE; - flags |= PIPE_CONTROL_CS_STALL; + bit_group_1 |= PIPE_CONTROL_CS_STALL; if (!HAS_3D_PIPELINE(engine->i915)) - flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; + bit_group_1 &= ~PIPE_CONTROL_3D_ARCH_FLAGS; else if (engine->class == COMPUTE_CLASS) - flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; + bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) return PTR_ERR(cs); - cs = gen12_emit_pipe_control(cs, - PIPE_CONTROL0_HDC_PIPELINE_FLUSH, - flags, LRC_PPHWSP_SCRATCH_ADDR); + cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1, + LRC_PPHWSP_SCRATCH_ADDR); intel_ring_advance(rq, cs); }
In preparation of the next patch allign with the datasheet (BSPEC 47112) with the naming of the pipe control set of flag values. The variable "flags" in gen12_emit_flush_rcs() is applied as a set of flags called Bit Group 1. Define also the Bit Group 0 as bit_group_0 where currently only PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.8+ --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +++++++++++++----------- 1 file changed, 18 insertions(+), 16 deletions(-)