From patchwork Thu Jul 27 05:35:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13328797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B17CC00528 for ; Thu, 27 Jul 2023 05:35:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 62FA710E0DC; Thu, 27 Jul 2023 05:35:47 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1251A10E0D6 for ; Thu, 27 Jul 2023 05:35:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690436146; x=1721972146; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s8YsLJg5dDLHw28kMnal3GDUP6BkhS5B2OJXZ1LDav0=; b=RxAiHXhMRxY+/xQ0gVD6W4KGdcvbn2vHJjJt/uDSk14eR4RkbxajILuc tr+8fhfaS4l9QIAXHARiOL0foGVfJBzc2bH2xy/cnV2M6A6WoCz94raqA uAc9GMwuxFveBT91s+DEe2x1tz7ohoMy5Dko0o9K9521HaLiYF92aIwZd WtmlAw7Cze6wCakH8ybEWjsYVp/SM9Vv2Fz9Jb6qbNoWbepVSYgTYE0DW cvyMTQSjvlReZsuHKMNa44AH2Gsg4wy95epLEFxzsAdKvd3OYiXLaXf4m qj7fTESrXsM7DFJUNsjel1idkD6dxKbILBMwmjfy4KIM3IBMbw6WHHko+ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="368227207" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="368227207" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jul 2023 22:35:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="676978335" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="676978335" Received: from vgrigo2x-mobl.ger.corp.intel.com (HELO jhogande-mobl1.ger.corp.intel.com) ([10.252.35.8]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jul 2023 22:35:44 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Date: Thu, 27 Jul 2023 08:35:16 +0300 Message-Id: <20230727053518.709345-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727053518.709345-1-jouni.hogander@intel.com> References: <20230727053518.709345-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v2 2/4] drm/i915/psr: Clear frontbuffer busy bits on flip X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are planning to move flush performed from work queue. This means it is possible to have invalidate -> flip -> flush sequence. Handle this by clearing possible busy bits on flip. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 04ab034a8d57..3a18334665fa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2230,6 +2230,12 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, if (crtc_state->crc_enabled && psr->enabled) psr_force_hw_tracking_exit(intel_dp); + /* + * Clear possible busy bits in case we have + * invalidate -> flip -> flush sequence. + */ + intel_dp->psr.busy_frontbuffer_bits = 0; + mutex_unlock(&psr->lock); } }