diff mbox series

[11/20] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also

Message ID 20230728041150.2524032-12-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series DSC misc fixes | expand

Commit Message

Ankit Nautiyal July 28, 2023, 4:11 a.m. UTC 
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.

For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++++++++---------
 1 file changed, 31 insertions(+), 17 deletions(-)

Comments

Stanislav Lisovskiy Aug. 7, 2023, 12:33 p.m. UTC | #1 
On Fri, Jul 28, 2023 at 09:41:41AM +0530, Ankit Nautiyal wrote:
> For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
> Check this condition for cases where bpc is forced by debugfs flag
> dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
> flag.
> 
> For MST case the pipe_bpp is already computed (hardcoded to be 24),
> and this check is not required.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++++++++---------
>  1 file changed, 31 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f41de126a8d3..78ac8f4fd348 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1697,6 +1697,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
>  	return 0;
>  }
>  
> +static
> +bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
> +{
> +	return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
> +}
> +
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config,
>  				struct drm_connector_state *conn_state,
> @@ -1708,7 +1714,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	const struct drm_display_mode *adjusted_mode =
>  		&pipe_config->hw.adjusted_mode;
> -	int pipe_bpp;
>  	int ret;
>  
>  	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> @@ -1720,28 +1725,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
>  		return -EINVAL;
>  
> -	if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
> -		pipe_bpp = intel_dp->force_dsc_bpc * 3;
> -		drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
> -			    intel_dp->force_dsc_bpc);
> -	} else if (compute_pipe_bpp) {
> -		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
> -	} else {
> -		pipe_bpp = pipe_config->pipe_bpp;
> -	}
> +	if (compute_pipe_bpp) {
> +		int pipe_bpp;
> +		int forced_bpp = intel_dp->force_dsc_bpc * 3;
>  
> -	if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Computed BPC less than min supported by source for DSC\n");
> -		return -EINVAL;
> +		if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
> +			pipe_bpp = forced_bpp;
> +			drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
> +				    intel_dp->force_dsc_bpc);
> +		} else {
> +			drm_WARN(&dev_priv->drm, forced_bpp,
> +				 "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
> +				 intel_dp->force_dsc_bpc);
> +
> +			pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> +							    conn_state->max_requested_bpc);
> +
> +			if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
> +				drm_dbg_kms(&dev_priv->drm,
> +					    "Computed BPC less than min supported by source for DSC\n");
> +				return -EINVAL;
> +			}
> +		}
> +
> +		pipe_config->pipe_bpp = pipe_bpp;
>  	}
>  
>  	/*
> -	 * For now enable DSC for max bpp, max link rate, max lane count.
> +	 * For now enable DSC for max link rate, max lane count.
>  	 * Optimize this later for the minimum possible link rate/lane count
>  	 * with DSC enabled for the requested mode.
>  	 */
> -	pipe_config->pipe_bpp = pipe_bpp;
>  	pipe_config->port_clock = limits->max_rate;
>  	pipe_config->lane_count = limits->max_lane_count;
>  
> @@ -1770,7 +1784,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  								    adjusted_mode->crtc_hdisplay,
>  								    pipe_config->bigjoiner_pipes,
>  								    pipe_config->output_format,
> -								    pipe_bpp,
> +								    pipe_config->pipe_bpp,
>  								    timeslots);
>  			if (!dsc_max_compressed_bpp) {
>  				drm_dbg_kms(&dev_priv->drm,
> -- 
> 2.40.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f41de126a8d3..78ac8f4fd348 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1697,6 +1697,12 @@  u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
 	return 0;
 }
 
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+	return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+}
+
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
@@ -1708,7 +1714,6 @@  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&pipe_config->hw.adjusted_mode;
-	int pipe_bpp;
 	int ret;
 
 	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1720,28 +1725,37 @@  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
 		return -EINVAL;
 
-	if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
-		pipe_bpp = intel_dp->force_dsc_bpc * 3;
-		drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
-			    intel_dp->force_dsc_bpc);
-	} else if (compute_pipe_bpp) {
-		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
-	} else {
-		pipe_bpp = pipe_config->pipe_bpp;
-	}
+	if (compute_pipe_bpp) {
+		int pipe_bpp;
+		int forced_bpp = intel_dp->force_dsc_bpc * 3;
 
-	if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Computed BPC less than min supported by source for DSC\n");
-		return -EINVAL;
+		if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
+			pipe_bpp = forced_bpp;
+			drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+				    intel_dp->force_dsc_bpc);
+		} else {
+			drm_WARN(&dev_priv->drm, forced_bpp,
+				 "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+				 intel_dp->force_dsc_bpc);
+
+			pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+							    conn_state->max_requested_bpc);
+
+			if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+				drm_dbg_kms(&dev_priv->drm,
+					    "Computed BPC less than min supported by source for DSC\n");
+				return -EINVAL;
+			}
+		}
+
+		pipe_config->pipe_bpp = pipe_bpp;
 	}
 
 	/*
-	 * For now enable DSC for max bpp, max link rate, max lane count.
+	 * For now enable DSC for max link rate, max lane count.
 	 * Optimize this later for the minimum possible link rate/lane count
 	 * with DSC enabled for the requested mode.
 	 */
-	pipe_config->pipe_bpp = pipe_bpp;
 	pipe_config->port_clock = limits->max_rate;
 	pipe_config->lane_count = limits->max_lane_count;
 
@@ -1770,7 +1784,7 @@  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 								    adjusted_mode->crtc_hdisplay,
 								    pipe_config->bigjoiner_pipes,
 								    pipe_config->output_format,
-								    pipe_bpp,
+								    pipe_config->pipe_bpp,
 								    timeslots);
 			if (!dsc_max_compressed_bpp) {
 				drm_dbg_kms(&dev_priv->drm,