| Message ID | 20230811044310.944883-4-alan.previn.teres.alexis@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/pxp/mtl: Update gsc-heci cmd submission | expand |
Hi Alan, kernel test robot noticed the following build warnings: [auto build test WARNING on 51fec314404b6a360493f225481083b2a664e3e1] url: https://github.com/intel-lab-lkp/linux/commits/Alan-Previn/drm-i915-pxp-mtl-Update-pxp-firmware-response-timeout/20230811-124534 base: 51fec314404b6a360493f225481083b2a664e3e1 patch link: https://lore.kernel.org/r/20230811044310.944883-4-alan.previn.teres.alexis%40intel.com patch subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/gt/pxp: User PXP contexts requires runalone bit in lrc config: i386-randconfig-r082-20230812 (https://download.01.org/0day-ci/archive/20230812/202308121007.jU4NvVxe-lkp@intel.com/config) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce: (https://download.01.org/0day-ci/archive/20230812/202308121007.jU4NvVxe-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202308121007.jU4NvVxe-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/gpu/drm/i915/gt/intel_lrc.c:851:34: sparse: sparse: dereference of noderef expression vim +851 drivers/gpu/drm/i915/gt/intel_lrc.c 847 848 static bool ctx_needs_runalone(const struct intel_context *ce) 849 { 850 if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) && > 851 ce->gem_context && ce->gem_context->uses_protected_content && 852 (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) 853 return true; 854 855 return false; 856 } 857
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 957d0aeb0c02..2dfa49a04172 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -845,6 +845,16 @@ lrc_setup_indirect_ctx(u32 *regs, lrc_ring_indirect_offset_default(engine) << 6; } +static bool ctx_needs_runalone(const struct intel_context *ce) +{ + if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) && + ce->gem_context && ce->gem_context->uses_protected_content && + (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) + return true; + + return false; +} + static void init_common_regs(u32 * const regs, const struct intel_context *ce, const struct intel_engine_cs *engine, @@ -860,6 +870,8 @@ static void init_common_regs(u32 * const regs, if (GRAPHICS_VER(engine->i915) < 11) ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | CTX_CTRL_RS_CTX_ENABLE); + if (ctx_needs_runalone(ce)) + ctl |= _MASKED_BIT_ENABLE(BIT(7)); regs[CTX_CONTEXT_CONTROL] = ctl; regs[CTX_TIMESTAMP] = ce->stats.runtime.last;
On Meteorlake onwards, HW specs require that all user contexts that run on render or compute engines and require PXP must enforce run-alone bit in lrc. Add this enforcement for protected contexts. Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)