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drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI

Message ID 20230814125241.234238-1-suraj.kandpal@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI | expand

Commit Message

Suraj Kandpal Aug. 14, 2023, 12:52 p.m. UTC 
Assign explicit value of 12 at 8bpp as per Table E2 of DSC 1.1 for DSI
panels even though we already use calculations from CModel for
first_line_bpg_offset.
The reason being some DSI monitors may have not have added the
change in errata for the calculation of first_line_bpg_offset.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9102
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Tested-by: William Tseng <william.tseng@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
 1 file changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ad6488e9c2b2..4646e00187c1 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1586,6 +1586,11 @@  static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
+	/* From Table E-2 in DSC 1.1*/
+	if (vdsc_cfg->dsc_version_minor == 1 &&
+	    vdsc_cfg->bits_per_pixel == 128)
+		vdsc_cfg->first_line_bpg_offset = 12;
+
 	/* DSI specific sanity checks on the common code */
 	drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
 	drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);