@@ -1798,16 +1798,68 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return 0;
}
-static void
+/**
+ * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
+ * @intel_dp: intel DP
+ * @crtc_state: crtc state
+ * @dsc: DSC compression mode
+ * @limits: link configuration limits
+ *
+ * Calculates the output link min, max bpp values in @limits based on the
+ * pipe bpp range, @crtc_state and @dsc mode.
+ *
+ * Returns %true in case of success.
+ */
+bool
+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dsc,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ int max_link_bpp;
+
+ max_link_bpp = limits->pipe.max_bpp << 4;
+
+ if (!dsc) {
+ max_link_bpp = rounddown(max_link_bpp, (2 * 3) << 4);
+
+ if (max_link_bpp < limits->pipe.min_bpp << 4)
+ return false;
+
+ limits->link.min_bpp = limits->pipe.min_bpp << 4;
+ } else {
+ limits->link.min_bpp = 0;
+ }
+
+ limits->link.max_bpp = max_link_bpp;
+
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp %d.%04d\n",
+ encoder->base.base.id, encoder->base.name,
+ crtc->base.base.id, crtc->base.name,
+ adjusted_mode->crtc_clock,
+ dsc ? "on" : "off",
+ limits->max_lane_count,
+ limits->max_rate,
+ limits->pipe.max_bpp,
+ limits->link.max_bpp >> 4,
+ (limits->link.max_bpp & 0xf) * 625);
+
+ return true;
+}
+
+static bool
intel_dp_compute_config_limits(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
bool respect_downstream_limits,
+ bool dsc,
struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
limits->min_rate = intel_dp_common_rate(intel_dp, 0);
limits->max_rate = intel_dp_max_link_rate(intel_dp);
@@ -1833,13 +1885,10 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- limits->link.min_bpp = limits->pipe.min_bpp << 4;
- limits->link.max_bpp = limits->pipe.max_bpp << 4;
-
- drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
- "max rate %d max bpp %d pixel clock %iKHz\n",
- limits->max_lane_count, limits->max_rate,
- limits->link.max_bpp >> 4, adjusted_mode->crtc_clock);
+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits);
}
static int
@@ -1858,9 +1907,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
- intel_dp_compute_config_limits(intel_dp, pipe_config,
- respect_downstream_limits, &limits);
-
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
@@ -1872,7 +1918,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
*/
joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
- dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
+ dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
+ !intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits,
+ false,
+ &limits);
if (!dsc_needed) {
/*
@@ -1889,6 +1939,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
+
+ if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits,
+ true,
+ &limits))
+ return -EINVAL;
+
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
conn_state, &limits, 64, true);
if (ret < 0)
@@ -151,4 +151,10 @@ void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
+bool
+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dsc,
+ struct link_config_limits *limits);
+
#endif /* __INTEL_DP_H__ */
@@ -305,9 +305,10 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
-static void
+static bool
intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
+ bool dsc,
struct link_config_limits *limits)
{
/*
@@ -333,8 +334,10 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- limits->link.min_bpp = limits->pipe.min_bpp << 4;
- limits->link.max_bpp = limits->pipe.max_bpp << 4;
+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits);
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
@@ -361,9 +364,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_mst_has_audio(conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
- intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
-
- dsc_needed = intel_dp->force_dsc_en;
+ dsc_needed = intel_dp->force_dsc_en ||
+ !intel_dp_mst_compute_config_limits(intel_dp,
+ pipe_config,
+ false,
+ &limits);
if (!dsc_needed) {
ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
@@ -382,6 +387,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
str_yes_no(ret),
str_yes_no(intel_dp->force_dsc_en));
+ if (!intel_dp_mst_compute_config_limits(intel_dp,
+ pipe_config,
+ true,
+ &limits))
+ return -EINVAL;
+
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp range, while in DSC mode it can be set in 1/16 bpp steps to any value up to the maximum pipe bpp. Update the limits accordingly in both modes to prepare for a follow-up patch which may need to reduce the max link bpp value and starts to check the link bpp limits in DSC mode as well. While at it add more detail to the link limit debug print and print it also for DSC mode. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 89 +++++++++++++++++---- drivers/gpu/drm/i915/display/intel_dp.h | 6 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 ++++-- 3 files changed, 96 insertions(+), 22 deletions(-)