@@ -3474,7 +3474,7 @@ int intel_dbuf_init(struct drm_i915_private *i915)
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3524,7 +3524,9 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- update_mbus_pre_enable(state);
+ if (hweight8(new_dbuf_state->active_pipes) <= hweight8(old_dbuf_state->active_pipes))
+ intel_dbuf_mbus_update(state);
+
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
@@ -3545,6 +3547,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ if (hweight8(new_dbuf_state->active_pipes) > hweight8(old_dbuf_state->active_pipes))
+ intel_dbuf_mbus_update(state);
+
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
According to BSpec we need to do correspondent MBUS updates before or after DBUF reallocation, depending on whether we are reducing or increasing amount of pipes(typical scenario is swithing between multiple and single displays). As of BSpec 49213 if we are swithing from multiple to single display MBUS registers should be updated with correspondent values _before_ Dbuf reallocation happens, however if we are switching from single display to multiple then it should happen _after_ DDB reallocation(i.e plane programming). Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)