From patchwork Wed Aug 23 17:07:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13362990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA675C71153 for ; Wed, 23 Aug 2023 17:10:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 69EDF10E4B5; Wed, 23 Aug 2023 17:09:37 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id D674B10E49E; Wed, 23 Aug 2023 17:09:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692810563; x=1724346563; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CUZ6cy5NoHam9afgdB3uxyLZHb1QdHNotMm1RFcIAuQ=; b=SmE6X+ox1b38cf+xotXl4o//zvzKkC4UzKTpNK9lVkn6L5bxwMCM5fJJ X6KzO9eiKdb6Vt6yByFGtfem2a4l5UAQVKiTjDMCygZ1RKPfTKj0z0d6F k34T+mw5cVDq8xxvRGg37Sl4bA5UCpSCq6E0TGCOvWb2nSzWHYSH3iagI 89BJd2OVJ0koB4n8DFNF0Jy2xtp4zH3y5YvihF8N9ow2cyPsrD4VjFaRS f+F0f02XicfYTgC2dhxLUDlDlDmcjoolT90vTeuFpo3kYpYt6qQn2UfoN dmEAKOgFFzvHvw2InWvjkE+XfXd/tM1tCVz+E9AoXBfyXvUoQScp96tfM g==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="438147520" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="438147520" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 10:09:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="802204892" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="802204892" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 10:09:23 -0700 From: Lucas De Marchi To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Wed, 23 Aug 2023 10:07:39 -0700 Message-Id: <20230823170740.1180212-42-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230823170740.1180212-1-lucas.demarchi@intel.com> References: <20230823170740.1180212-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Stanislav Lisovskiy According to BSpec we need to write the MBUS CTL and DBUF CTL both for increasing CDCLK case (pre plane) and for decreasing CDCLK case (post plane). Make sure those updates are in place for Xe2-LPD. Since the mbus update is not only on pre-enable anymore, also rename the function accordingly. Cc: Mika Kahola Signed-off-by: Stanislav Lisovskiy Signed-off-by: Lucas De Marchi Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 79454b4d99e3..77a4c85538c2 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3493,7 +3493,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915, * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before * update the request state of all DBUS slices. */ -static void update_mbus_pre_enable(struct intel_atomic_state *state) +static void update_mbus(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); u32 mbus_ctl, dbuf_min_tracker_val; @@ -3552,7 +3552,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); - update_mbus_pre_enable(state); + update_mbus(state); gen9_dbuf_slices_update(i915, old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices); @@ -3574,6 +3574,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); + if (DISPLAY_VER(i915) >= 20) + update_mbus(state); + gen9_dbuf_slices_update(i915, new_dbuf_state->enabled_slices); }