| Message ID | 20230824080517.693621-15-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Improve BW management on shared display links | expand |
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 6eeb7dbf5ba67..930e16b870734 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -111,7 +111,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, dsc ? bpp << 4 : bpp, dsc, - false); + (dsc || crtc_state->fec_enable) && + !intel_dp_is_uhbr(crtc_state)); slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, connector->port,
On 8b/10b MST links the PBN value for DSC streams must be calculated accounting for the FEC overhead. The same applies to 8b/10b non-DSC streams if there is another DSC stream on the same link. Fix up the PBN calculation accordingly. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)