From patchwork Thu Aug 24 08:05:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13363745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBE64C83003 for ; Thu, 24 Aug 2023 08:05:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6040B10E4F7; Thu, 24 Aug 2023 08:05:36 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D2B210E4F9 for ; Thu, 24 Aug 2023 08:05:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692864329; x=1724400329; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=4OpeodefDWzI8YvUEefqmEu9/Pn1R3XYKqn6kDI4eQ8=; b=cqnWR/AKrTJDIUMcozmQTrXevB2wPaRcm3XWwqHLMkCobDNbko+hesRV FiLHjiT1WgR57duGz5wq7Va/smBeDG6NAw8NPbeMOX7w9+m+VNNwkJUbp kKdAe/mHSEUz6fJa+0gp/0avpeyYmc1/AWVXfiC1H8C5Dl4WdSAYTin7Z FIjShxN2UhilC+B0K6xrgF301U/tSqV3bqnr5GNQg8/qq5Jgs5yN7Nuh4 gLcsYE46pIdkiJi2LESqh4SD5mAKMzMYS3giZcJptSVHCtZX/NT7nQU5C j1vI36hfPg1Yy+Az8ToE8iCK8H3HQ837SKQEg5Q0ZFgrNpkTgQkqDePMY A==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="374345913" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="374345913" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 01:05:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="880710366" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 01:05:33 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 11:05:17 +0300 Message-Id: <20230824080517.693621-23-imre.deak@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230824080517.693621-1-imre.deak@intel.com> References: <20230824080517.693621-1-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After the previous patch the BW limits on the whole MST topology will be checked after computing the state for all the streams in the topology. Accordingly remove the check during the stream's encoder compute config step, to prevent failing an atomic commit due to a BW limit, if this can be resolved only by reducing the BW of other streams on the same MST link. Signed-off-by: Imre Deak Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 3c9b3a2ac88a2..1d6d0fe6c3047 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -121,15 +121,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, if (slots == -EDEADLK) return slots; - if (slots >= 0) { - ret = drm_dp_mst_atomic_check(state); - /* - * If we got slots >= 0 and we can fit those based on check - * then we can exit the loop. Otherwise keep trying. - */ - if (!ret) - break; - } + if (slots >= 0) + break; } /* We failed to find a proper bpp/timeslots, return error */