From patchwork Mon Aug 28 05:43:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13367555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63AC2C83F16 for ; Mon, 28 Aug 2023 05:45:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 00DF510E17B; Mon, 28 Aug 2023 05:44:59 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id F199F10E125 for ; Mon, 28 Aug 2023 05:44:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693201496; x=1724737496; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o/vo5jmSousUBY2KUyFUYL8vaumAywWkHtryZWDeE9s=; b=YqvywGs0p3p/3Q6G8MYIwq7fdMjua7d2g5ASEoRmNuVsbXx6ya4O735Z 5/pQuVyvSyJ3lc1zw5O2Rbxe25FrDKiu2SSZtxPP+ulQnDBZQxX7il8mW srlCYIGLJmyjCIwhAcZvMcG6vbQwhAaSYIAqyM5XktODqXmeBZccZ6HlG QJqmL5Wtawhvz5dQmMZlEjnukAqk8yPbYFnGPLhyUSo9+0wej0AYwaUP0 vzAXCU0NVZfu76Z+K8bLu6xJp0s/yYdwbX+StgN7F2Dt34NIjFdKYL6tl jxVH4w/q03g/2bIm1xw5dcFzqB8PDw/5EUTxCRqyg9FA3CUe/r7E/dbkw w==; X-IronPort-AV: E=McAfee;i="6600,9927,10815"; a="373906644" X-IronPort-AV: E=Sophos;i="6.02,206,1688454000"; d="scan'208";a="373906644" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2023 22:44:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10815"; a="738128619" X-IronPort-AV: E=Sophos;i="6.02,206,1688454000"; d="scan'208";a="738128619" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by orsmga002.jf.intel.com with ESMTP; 27 Aug 2023 22:44:54 -0700 From: Suraj Kandpal To: intel-gfx@lists.freedesktop.org Date: Mon, 28 Aug 2023 11:13:00 +0530 Message-Id: <20230828054300.560559-8-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230828054300.560559-1-suraj.kandpal@intel.com> References: <20230828054300.560559-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v12 7/8] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We have setup both the read and write functions so we can move ahead and fill in all the readout state from PPS register into the crtc_state so we can send it for comparision. --v2 -Shorten comment to just PPSX rather than having the whole "Readout PPSX register" [Jani] -Remove pps_temp reinitialization as its being initialized in the read function [Jani] -Use REG_FIELD_GET to readout certain fields of dsc registers [Jani] --v9 -Place the masks at a more appropriate place [Ankit] Signed-off-by: Suraj Kandpal Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 100 ++++++++++++++++-- .../gpu/drm/i915/display/intel_vdsc_regs.h | 2 + 2 files changed, 95 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 7dfc87421b92..b24601d0b2c5 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -852,20 +852,106 @@ static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_stat static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) { struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; - u32 pps_temp1, pps_temp2; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); + u32 pps_temp; + + /* PPS_0 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp); - /* FIXME: add more state readout as needed */ + vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT; + vdsc_cfg->line_buf_depth = + (pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT; + vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION; + vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION; + vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE; + vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE; + vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE; + vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE; - /* Readout PPS_0 and PPS_1 registers */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1); - intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2); + /* PPS_1 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp); - vdsc_cfg->bits_per_pixel = pps_temp2; + vdsc_cfg->bits_per_pixel = pps_temp; - if (pps_temp1 & DSC_NATIVE_420_ENABLE) + if (vdsc_cfg->native_420) vdsc_cfg->bits_per_pixel >>= 1; crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; + + /* PPS_2 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp); + + vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances; + vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp); + + /* PPS_3 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp); + + vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp); + vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp); + + /* PPS_4 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp); + + vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp); + vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp); + + /* PPS_5 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp); + + vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp); + vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp); + + /* PPS_6 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp); + + vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp); + vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp); + vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp); + + /* PPS_7 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp); + + vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp); + + /* PPS_8 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp); + + vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp); + vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp); + + /* PPS_9 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp); + + vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp); + + /* PPS_10 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp); + + vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp); + vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp); + + /* PPS_16 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp); + + vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp); + + if (DISPLAY_VER(i915) >= 14) { + /* PPS_17 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp); + + vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp); + + /* PPS_18 */ + intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp); + + vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp); + } } void intel_dsc_get_config(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 4c9a51df4775..5cbcbd9db7b1 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -81,7 +81,9 @@ #define DSC_COLOR_SPACE_CONVERSION (1 << 17) #define DSC_BLOCK_PREDICTION (1 << 16) #define DSC_LINE_BUF_DEPTH_SHIFT 12 +#define DSC_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) #define DSC_BPC_SHIFT 8 +#define DSC_BPC_MASK REG_GENMASK(11, 8) #define DSC_VER_MIN_SHIFT 4 #define DSC_VER_MAJ (0x1 << 0)