diff mbox series

[v4,2/3] drm/i915/pxp/mtl: Update pxp-firmware packet size

Message ID 20230907001549.81262-3-alan.previn.teres.alexis@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec | expand

Commit Message

Teres Alexis, Alan Previn Sept. 7, 2023, 12:15 a.m. UTC
Update the GSC-fw input/output HECI packet size to match
updated internal fw specs.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Teres Alexis, Alan Previn Sept. 7, 2023, 5:16 a.m. UTC | #1
On Wed, 2023-09-06 at 17:15 -0700, Teres Alexis, Alan Previn wrote:
> Update the GSC-fw input/output HECI packet size to match
> updated internal fw specs.
alan:snip

> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
> @@ -14,8 +14,8 @@
> 


> +/* PXP-Packet sizes for MTL's GSCCS-HECI instruction is 65K*/
> +#define PXP43_MAX_HECI_INOUT_SIZE (SZ_64K + SZ_1K)
alan: my mistake - didnt fix this before posting - should have been PAGE_ALIGN(65k)
Balasubrawmanian, Vivaik Sept. 15, 2023, 5:30 p.m. UTC | #2
On 9/14/2023 3:28 PM, Balasubrawmanian, Vivaik wrote:
> On 9/6/2023 5:15 PM, Alan Previn wrote:
>> Update the GSC-fw input/output HECI packet size to match
>> updated internal fw specs.
>>
>> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
>> ---
>>   drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h 
>> b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
>> index 0165d38fbead..b2196b008f26 100644
>> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
>> @@ -14,8 +14,8 @@
>>   #define PXP43_CMDID_NEW_HUC_AUTH 0x0000003F /* MTL+ */
>>   #define PXP43_CMDID_INIT_SESSION 0x00000036
>>   -/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
>> -#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K)
>> +/* PXP-Packet sizes for MTL's GSCCS-HECI instruction is 65K*/
>> +#define PXP43_MAX_HECI_INOUT_SIZE (SZ_64K + SZ_1K)
>>     /* PXP-Packet size for MTL's NEW_HUC_AUTH instruction */
>>   #define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K)
>
> Reviewed-by: Balasubrawmanian, Vivaik 
> <vivaik.balasubrawmanian@intel.com> 
> <mailto:vivaik.balasubrawmanian@intel.com>
>
Balasubrawmanian, Vivaik Sept. 15, 2023, 5:49 p.m. UTC | #3
On 9/14/2023 3:28 PM, Balasubrawmanian, Vivaik wrote:
> On 9/6/2023 5:15 PM, Alan Previn wrote:
>> Update the GSC-fw input/output HECI packet size to match
>> updated internal fw specs.
>>
>> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
>> ---
>>   drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h 
>> b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
>> index 0165d38fbead..b2196b008f26 100644
>> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
>> @@ -14,8 +14,8 @@
>>   #define PXP43_CMDID_NEW_HUC_AUTH 0x0000003F /* MTL+ */
>>   #define PXP43_CMDID_INIT_SESSION 0x00000036
>>   -/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
>> -#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K)
>> +/* PXP-Packet sizes for MTL's GSCCS-HECI instruction is 65K*/
>> +#define PXP43_MAX_HECI_INOUT_SIZE (SZ_64K + SZ_1K)
>>     /* PXP-Packet size for MTL's NEW_HUC_AUTH instruction */
>>   #define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K)
>
> Reviewed-by: Balasubrawmanian, Vivaik 
> <vivaik.balasubrawmanian@intel.com> 
> <mailto:vivaik.balasubrawmanian@intel.com>
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
index 0165d38fbead..b2196b008f26 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
@@ -14,8 +14,8 @@ 
 #define PXP43_CMDID_NEW_HUC_AUTH 0x0000003F /* MTL+ */
 #define PXP43_CMDID_INIT_SESSION 0x00000036
 
-/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
-#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K)
+/* PXP-Packet sizes for MTL's GSCCS-HECI instruction is 65K*/
+#define PXP43_MAX_HECI_INOUT_SIZE (SZ_64K + SZ_1K)
 
 /* PXP-Packet size for MTL's NEW_HUC_AUTH instruction */
 #define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K)