diff mbox series

[1/2] drm/i915: Check lane count when determining FEC support

Message ID 20230913150356.9477-1-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915: Check lane count when determining FEC support | expand

Commit Message

Ville Syrjälä Sept. 13, 2023, 3:03 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ICL doesn't support FEC with a x1 DP link. Make sure
we don't try to enable FEC in such cases.

Requires a bit of reordering to make sure we've computed lane_count
before checking it.

Cc: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

Comments

Jani Nikula Sept. 20, 2023, 9:23 a.m. UTC | #1 
On Wed, 13 Sep 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ICL doesn't support FEC with a x1 DP link. Make sure
> we don't try to enable FEC in such cases.

The question is, should we rather require x2 link for FEC?

I suppose x1 link with DSC+FEC is an unlikely scenario with our current
link bandwidth policy, so probably not a big deal.

BR,
Jani.

>
> Requires a bit of reordering to make sure we've computed lane_count
> before checking it.
>
> Cc: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++----------
>  1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 55ba6eeaa810..2cde8ac513bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1363,7 +1363,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
>  	if (DISPLAY_VER(dev_priv) >= 12)
>  		return true;
>  
> -	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> +	if (DISPLAY_VER(dev_priv) == 11 &&
> +	    encoder->port != PORT_A && pipe_config->lane_count != 1)
>  		return true;
>  
>  	return false;
> @@ -2105,15 +2106,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  		&pipe_config->hw.adjusted_mode;
>  	int ret;
>  
> -	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> -		intel_dp_supports_fec(intel_dp, pipe_config);
> -
> -	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> -		return -EINVAL;
> -
> -	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> -		return -EINVAL;
> -
>  	/*
>  	 * compute pipe bpp is set to false for DP MST DSC case
>  	 * and compressed_bpp is calculated same time once
> @@ -2134,6 +2126,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  		}
>  	}
>  
> +	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> +		intel_dp_supports_fec(intel_dp, pipe_config);
> +
> +	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> +		return -EINVAL;
> +
> +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> +		return -EINVAL;
> +
>  	/* Calculate Slice count */
>  	if (intel_dp_is_edp(intel_dp)) {
>  		pipe_config->dsc.slice_count =
Ville Syrjälä Sept. 20, 2023, 11:14 a.m. UTC | #2 
On Wed, Sep 20, 2023 at 12:23:34PM +0300, Jani Nikula wrote:
> On Wed, 13 Sep 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > ICL doesn't support FEC with a x1 DP link. Make sure
> > we don't try to enable FEC in such cases.
> 
> The question is, should we rather require x2 link for FEC?
> 
> I suppose x1 link with DSC+FEC is an unlikely scenario with our current
> link bandwidth policy, so probably not a big deal.

I think currently we just smash lane_count to max when using DSC.
So doesn't really matter currently. But something to keep in mind 
if/when we tune the policy.

> 
> BR,
> Jani.
> 
> >
> > Requires a bit of reordering to make sure we've computed lane_count
> > before checking it.
> >
> > Cc: Luca Coelho <luciano.coelho@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++----------
> >  1 file changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 55ba6eeaa810..2cde8ac513bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1363,7 +1363,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> >  	if (DISPLAY_VER(dev_priv) >= 12)
> >  		return true;
> >  
> > -	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> > +	if (DISPLAY_VER(dev_priv) == 11 &&
> > +	    encoder->port != PORT_A && pipe_config->lane_count != 1)
> >  		return true;
> >  
> >  	return false;
> > @@ -2105,15 +2106,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  		&pipe_config->hw.adjusted_mode;
> >  	int ret;
> >  
> > -	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > -		intel_dp_supports_fec(intel_dp, pipe_config);
> > -
> > -	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > -		return -EINVAL;
> > -
> > -	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > -		return -EINVAL;
> > -
> >  	/*
> >  	 * compute pipe bpp is set to false for DP MST DSC case
> >  	 * and compressed_bpp is calculated same time once
> > @@ -2134,6 +2126,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  		}
> >  	}
> >  
> > +	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > +		intel_dp_supports_fec(intel_dp, pipe_config);
> > +
> > +	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > +		return -EINVAL;
> > +
> > +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > +		return -EINVAL;
> > +
> >  	/* Calculate Slice count */
> >  	if (intel_dp_is_edp(intel_dp)) {
> >  		pipe_config->dsc.slice_count =
> 
> -- 
> Jani Nikula, Intel
Jani Nikula Sept. 20, 2023, 12:01 p.m. UTC | #3 
On Wed, 20 Sep 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Sep 20, 2023 at 12:23:34PM +0300, Jani Nikula wrote:
>> On Wed, 13 Sep 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > ICL doesn't support FEC with a x1 DP link. Make sure
>> > we don't try to enable FEC in such cases.
>> 
>> The question is, should we rather require x2 link for FEC?
>> 
>> I suppose x1 link with DSC+FEC is an unlikely scenario with our current
>> link bandwidth policy, so probably not a big deal.
>
> I think currently we just smash lane_count to max when using DSC.
> So doesn't really matter currently. But something to keep in mind 
> if/when we tune the policy.

The patch is actually a bit subtle. Or the existing code is.

The paths under intel_edp_dsc_compute_pipe_bpp() and
intel_dp_dsc_compute_pipe_bpp() *assume* FEC is enabled/disabled
depending on the case. They don't look at fec_enable. Any checks for
fec_enable in there would be late.

Let's say eDP gains the ability to do FEC. I don't even remember what
the DP spec says about that. But having to check for fec_enable would
trip over, because it's not initialized yet.

So the patch highlights one aspect to keep in mind, but a little bit
hides another point to keep in mind. Damned if you do, damned if you
don't...

BR,
Jani.


>
>> 
>> BR,
>> Jani.
>> 
>> >
>> > Requires a bit of reordering to make sure we've computed lane_count
>> > before checking it.
>> >
>> > Cc: Luca Coelho <luciano.coelho@intel.com>
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++----------
>> >  1 file changed, 11 insertions(+), 10 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 55ba6eeaa810..2cde8ac513bb 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -1363,7 +1363,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
>> >  	if (DISPLAY_VER(dev_priv) >= 12)
>> >  		return true;
>> >  
>> > -	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
>> > +	if (DISPLAY_VER(dev_priv) == 11 &&
>> > +	    encoder->port != PORT_A && pipe_config->lane_count != 1)
>> >  		return true;
>> >  
>> >  	return false;
>> > @@ -2105,15 +2106,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>> >  		&pipe_config->hw.adjusted_mode;
>> >  	int ret;
>> >  
>> > -	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
>> > -		intel_dp_supports_fec(intel_dp, pipe_config);
>> > -
>> > -	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> > -		return -EINVAL;
>> > -
>> > -	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
>> > -		return -EINVAL;
>> > -
>> >  	/*
>> >  	 * compute pipe bpp is set to false for DP MST DSC case
>> >  	 * and compressed_bpp is calculated same time once
>> > @@ -2134,6 +2126,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>> >  		}
>> >  	}
>> >  
>> > +	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
>> > +		intel_dp_supports_fec(intel_dp, pipe_config);
>> > +
>> > +	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> > +		return -EINVAL;
>> > +
>> > +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
>> > +		return -EINVAL;
>> > +
>> >  	/* Calculate Slice count */
>> >  	if (intel_dp_is_edp(intel_dp)) {
>> >  		pipe_config->dsc.slice_count =
>> 
>> -- 
>> Jani Nikula, Intel
Imre Deak Oct. 5, 2023, 1:13 p.m. UTC | #4 
On Wed, Sep 13, 2023 at 06:03:55PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> ICL doesn't support FEC with a x1 DP link. Make sure
> we don't try to enable FEC in such cases.
> 
> Requires a bit of reordering to make sure we've computed lane_count
> before checking it.
> 
> Cc: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++----------
>  1 file changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 55ba6eeaa810..2cde8ac513bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1363,7 +1363,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
>  	if (DISPLAY_VER(dev_priv) >= 12)
>  		return true;
>  
> -	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> +	if (DISPLAY_VER(dev_priv) == 11 &&
> +	    encoder->port != PORT_A && pipe_config->lane_count != 1)
>  		return true;
>  
>  	return false;
> @@ -2105,15 +2106,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  		&pipe_config->hw.adjusted_mode;
>  	int ret;
>  
> -	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> -		intel_dp_supports_fec(intel_dp, pipe_config);
> -
> -	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> -		return -EINVAL;
> -
> -	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> -		return -EINVAL;
> -
>  	/*
>  	 * compute pipe bpp is set to false for DP MST DSC case
>  	 * and compressed_bpp is calculated same time once
> @@ -2134,6 +2126,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  		}
>  	}
>  
> +	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> +		intel_dp_supports_fec(intel_dp, pipe_config);
> +
> +	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> +		return -EINVAL;
> +
> +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> +		return -EINVAL;
> +
>  	/* Calculate Slice count */
>  	if (intel_dp_is_edp(intel_dp)) {
>  		pipe_config->dsc.slice_count =
> -- 
> 2.41.0
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 55ba6eeaa810..2cde8ac513bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1363,7 +1363,8 @@  static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 	if (DISPLAY_VER(dev_priv) >= 12)
 		return true;
 
-	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
+	if (DISPLAY_VER(dev_priv) == 11 &&
+	    encoder->port != PORT_A && pipe_config->lane_count != 1)
 		return true;
 
 	return false;
@@ -2105,15 +2106,6 @@  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 		&pipe_config->hw.adjusted_mode;
 	int ret;
 
-	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
-		intel_dp_supports_fec(intel_dp, pipe_config);
-
-	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
-		return -EINVAL;
-
-	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
-		return -EINVAL;
-
 	/*
 	 * compute pipe bpp is set to false for DP MST DSC case
 	 * and compressed_bpp is calculated same time once
@@ -2134,6 +2126,15 @@  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 		}
 	}
 
+	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+		intel_dp_supports_fec(intel_dp, pipe_config);
+
+	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
+		return -EINVAL;
+
+	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+		return -EINVAL;
+
 	/* Calculate Slice count */
 	if (intel_dp_is_edp(intel_dp)) {
 		pipe_config->dsc.slice_count =