diff mbox series

[5/5] drm/i915/fbc: Split plane pixel format checks per-platform

Message ID 20230914113854.10008-5-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/5] drm/i915/fbc: Remove ancient 16k plane stride limit | expand

Commit Message

Ville Syrjälä Sept. 14, 2023, 11:38 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Carve up pixel_format_is_valid() into per-platform variants to
make it easier to see what limits are actually being imposed.

Note that the XRGB1555 can be dropped from the g4x+ variant
since the plane no longer supports that format anyway.

TODO: maybe go for vfuncs later

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 28 +++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

Comments

Govindapillai, Vinod Oct. 1, 2023, 11:08 a.m. UTC | #1 
On Thu, 2023-09-14 at 14:38 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Carve up pixel_format_is_valid() into per-platform variants to
> make it easier to see what limits are actually being imposed.
> 
> Note that the XRGB1555 can be dropped from the g4x+ variant
> since the plane no longer supports that format anyway.
> 
> TODO: maybe go for vfuncs later
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 28 +++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1a6931e66d5d..51998b1ec941 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -912,7 +912,7 @@ static bool stride_is_valid(const struct intel_plane_state *plane_state)
>                 return i8xx_fbc_stride_is_valid(plane_state);
>  }
>  
> -static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
> +static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
>  {
>         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
>         const struct drm_framebuffer *fb = plane_state->hw.fb;
> @@ -926,6 +926,22 @@ static bool pixel_format_is_valid(const struct intel_plane_state
> *plane_state)
>                 /* 16bpp not supported on gen2 */
>                 if (DISPLAY_VER(i915) == 2)
>                         return false;
> +               return true;
> +       default:
> +               return false;
> +       }
> +}
> +
> +static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
> +{
> +       struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> +       const struct drm_framebuffer *fb = plane_state->hw.fb;
> +
> +       switch (fb->format->format) {
> +       case DRM_FORMAT_XRGB8888:
> +       case DRM_FORMAT_XBGR8888:
> +               return true;
> +       case DRM_FORMAT_RGB565:
>                 /* WaFbcOnly1to1Ratio:ctg */
>                 if (IS_G4X(i915))
>                         return false;
> @@ -935,6 +951,16 @@ static bool pixel_format_is_valid(const struct intel_plane_state
> *plane_state)
>         }
>  }
>  
> +static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
> +{
> +       struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> +
> +       if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
> +               return g4x_fbc_pixel_format_is_valid(plane_state);
> +       else
> +               return i8xx_fbc_pixel_format_is_valid(plane_state);
> +}
> +
>  static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
>  {
>         return plane_state->hw.rotation == DRM_MODE_ROTATE_0;
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1a6931e66d5d..51998b1ec941 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -912,7 +912,7 @@  static bool stride_is_valid(const struct intel_plane_state *plane_state)
 		return i8xx_fbc_stride_is_valid(plane_state);
 }
 
-static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
+static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -926,6 +926,22 @@  static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
 		/* 16bpp not supported on gen2 */
 		if (DISPLAY_VER(i915) == 2)
 			return false;
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_XBGR8888:
+		return true;
+	case DRM_FORMAT_RGB565:
 		/* WaFbcOnly1to1Ratio:ctg */
 		if (IS_G4X(i915))
 			return false;
@@ -935,6 +951,16 @@  static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
 	}
 }
 
+static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+
+	if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
+		return g4x_fbc_pixel_format_is_valid(plane_state);
+	else
+		return i8xx_fbc_pixel_format_is_valid(plane_state);
+}
+
 static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
 {
 	return plane_state->hw.rotation == DRM_MODE_ROTATE_0;