| Message ID | 20230919114716.19378-1-nirmoy.das@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Fix aux invalidation with proper pipe_control flag | expand |
Hi Nirmoy, On Tue, Sep 19, 2023 at 01:47:16PM +0200, Nirmoy Das wrote: > The suggestion from the spec is to do l3 fabric flush not L3 flush. > > Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before > invalidation") please put this in one line. > Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> > Cc: Andi Shyti <andi.shyti@linux.intel.com> > Cc: <stable@vger.kernel.org> # v5.8+ > Cc: Nirmoy Das <nirmoy.das@intel.com> > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> > Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> and I believe Tested-by: Tapani Pälli <tapani.palli@intel.com> Thanks, Andi
On 19.9.2023 15.11, Andi Shyti wrote: > Hi Nirmoy, > > On Tue, Sep 19, 2023 at 01:47:16PM +0200, Nirmoy Das wrote: >> The suggestion from the spec is to do l3 fabric flush not L3 flush. >> >> Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before >> invalidation") > please put this in one line. > >> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> >> Cc: Andi Shyti <andi.shyti@linux.intel.com> >> Cc: <stable@vger.kernel.org> # v5.8+ >> Cc: Nirmoy Das <nirmoy.das@intel.com> >> Cc: Andrzej Hajda <andrzej.hajda@intel.com> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Matt Roper <matthew.d.roper@intel.com> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com> >> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> >> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> >> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> > > and I believe > > Tested-by: Tapani Pälli <tapani.palli@intel.com> Yes, tested on TGL LP (0x9a49)! > Thanks, > Andi
On 19.09.2023 13:47, Nirmoy Das wrote: > The suggestion from the spec is to do l3 fabric flush not L3 flush. > > Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before > invalidation") > Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> > Cc: Andi Shyti <andi.shyti@linux.intel.com> > Cc: <stable@vger.kernel.org> # v5.8+ > Cc: Nirmoy Das <nirmoy.das@intel.com> > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> > Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Regards Andrzej > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +++++- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index 0143445dba83..a4b241d502c8 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -272,7 +272,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; > > bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; > - bit_group_1 |= PIPE_CONTROL_FLUSH_L3; > + if (mode & EMIT_FLUSH) > + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; > + else if (gen12_needs_ccs_aux_inv(engine)) > + bit_group_1 |= PIPE_CONTROL_L3_FABRIC_FLUSH; > + > bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > /* Wa_1409600907:tgl,adl-p */ > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 2bd8d98d2110..12e8dc481c53 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -284,6 +284,7 @@ > #define DISPLAY_PLANE_A (0<<20) > #define DISPLAY_PLANE_B (1<<20) > #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) > +#define PIPE_CONTROL_L3_FABRIC_FLUSH (1<<30) > #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */ > #define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */ > #define PIPE_CONTROL_FLUSH_L3 (1<<27)
Sent out https://patchwork.freedesktop.org/series/123975/ to replace this one as this not really fixing the issue. Thanks, Nirmoy On 9/19/2023 2:19 PM, Tapani Pälli wrote: > > On 19.9.2023 15.11, Andi Shyti wrote: >> Hi Nirmoy, >> >> On Tue, Sep 19, 2023 at 01:47:16PM +0200, Nirmoy Das wrote: >>> The suggestion from the spec is to do l3 fabric flush not L3 flush. >>> >>> Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before >>> invalidation") >> please put this in one line. >> >>> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> >>> Cc: Andi Shyti <andi.shyti@linux.intel.com> >>> Cc: <stable@vger.kernel.org> # v5.8+ >>> Cc: Nirmoy Das <nirmoy.das@intel.com> >>> Cc: Andrzej Hajda <andrzej.hajda@intel.com> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>> Cc: Matt Roper <matthew.d.roper@intel.com> >>> Cc: Lucas De Marchi <lucas.demarchi@intel.com> >>> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> >>> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> >>> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> >> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> >> >> and I believe >> >> Tested-by: Tapani Pälli <tapani.palli@intel.com> > > Yes, tested on TGL LP (0x9a49)! > > >> Thanks, >> Andi
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 0143445dba83..a4b241d502c8 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -272,7 +272,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; - bit_group_1 |= PIPE_CONTROL_FLUSH_L3; + if (mode & EMIT_FLUSH) + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; + else if (gen12_needs_ccs_aux_inv(engine)) + bit_group_1 |= PIPE_CONTROL_L3_FABRIC_FLUSH; + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; /* Wa_1409600907:tgl,adl-p */ diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 2bd8d98d2110..12e8dc481c53 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -284,6 +284,7 @@ #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) +#define PIPE_CONTROL_L3_FABRIC_FLUSH (1<<30) #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */ #define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */ #define PIPE_CONTROL_FLUSH_L3 (1<<27)
The suggestion from the spec is to do l3 fabric flush not L3 flush. Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before invalidation") Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Cc: Nirmoy Das <nirmoy.das@intel.com> Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +++++- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-)