| Message ID | 20230920040547.181861-1-shekhar.chauhan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Add Wa_18028616096 | expand |
Hi Shekhar,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Shekhar-Chauhan/drm-i915-Add-Wa_18028616096/20230920-121417
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230920040547.181861-1-shekhar.chauhan%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096
config: x86_64-randconfig-003-20230920 (https://download.01.org/0day-ci/archive/20230920/202309201405.PF0VVCts-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230920/202309201405.PF0VVCts-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309201405.PF0VVCts-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from include/linux/container_of.h:5,
from include/linux/plist.h:76,
from include/linux/pm_qos.h:15,
from drivers/gpu/drm/i915/i915_drv.h:35,
from drivers/gpu/drm/i915/gt/intel_workarounds.c:6:
drivers/gpu/drm/i915/gt/intel_workarounds.c: In function 'general_render_compute_wa_init':
>> include/linux/build_bug.h:16:51: error: negative width in bit-field '<anonymous>'
16 | #define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); })))
| ^
drivers/gpu/drm/i915/i915_reg_defs.h:22:16: note: in expansion of macro 'BUILD_BUG_ON_ZERO'
22 | BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gt/intel_gt_regs.h:1232:49: note: in expansion of macro 'REG_BIT'
1232 | #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58)
| ^~~~~~~
drivers/gpu/drm/i915/gt/intel_workarounds.c:2919:57: note: in expansion of macro 'UGM_FRAGMENT_THRESHOLD_TO_3'
2919 | wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, UGM_FRAGMENT_THRESHOLD_TO_3);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +16 include/linux/build_bug.h
bc6245e5efd70c Ian Abbott 2017-07-10 6
bc6245e5efd70c Ian Abbott 2017-07-10 7 #ifdef __CHECKER__
bc6245e5efd70c Ian Abbott 2017-07-10 8 #define BUILD_BUG_ON_ZERO(e) (0)
bc6245e5efd70c Ian Abbott 2017-07-10 9 #else /* __CHECKER__ */
bc6245e5efd70c Ian Abbott 2017-07-10 10 /*
bc6245e5efd70c Ian Abbott 2017-07-10 11 * Force a compilation error if condition is true, but also produce a
8788994376d84d Rikard Falkeborn 2019-12-04 12 * result (of value 0 and type int), so the expression can be used
bc6245e5efd70c Ian Abbott 2017-07-10 13 * e.g. in a structure initializer (or where-ever else comma expressions
bc6245e5efd70c Ian Abbott 2017-07-10 14 * aren't permitted).
bc6245e5efd70c Ian Abbott 2017-07-10 15 */
8788994376d84d Rikard Falkeborn 2019-12-04 @16 #define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); })))
527edbc18a70e7 Masahiro Yamada 2019-01-03 17 #endif /* __CHECKER__ */
527edbc18a70e7 Masahiro Yamada 2019-01-03 18
Quoting Shekhar Chauhan (2023-09-20 01:05:47-03:00) >Drop UGM per set fragment threshold to 3 > >BSpec: 54833 >Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> >--- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 4 insertions(+) > >diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >index a00ff51c681d..f8ab99affa15 100644 >--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h >+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >@@ -1227,6 +1227,7 @@ > #define EU_PERF_CNTL3 PERF_REG(0xe758) > > #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) >+#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58) You probably want to define this as: #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) , and after the definition of LSC_CHICKEN_BIT_0_UDW. See more below... > #define DISABLE_D8_D16_COASLESCE REG_BIT(30) > #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) > #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >index 660d4f358eab..3f3977014ee7 100644 >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >@@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > * Wa_22015475538:dg2 > */ > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); >+ >+ /* Wa_18028616096:dg2 */ >+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, UGM_FRAGMENT_THRESHOLD_TO_3); ...and here, use LSC_CHICKEN_BIT_0_UDW as target. -- Gustavo Sousa > } > > if (IS_DG2_G11(i915)) { >-- >2.34.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a00ff51c681d..f8ab99affa15 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1227,6 +1227,7 @@ #define EU_PERF_CNTL3 PERF_REG(0xe758) #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) +#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58) #define DISABLE_D8_D16_COASLESCE REG_BIT(30) #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 660d4f358eab..3f3977014ee7 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18028616096:dg2 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, UGM_FRAGMENT_THRESHOLD_TO_3); } if (IS_DG2_G11(i915)) {
Drop UGM per set fragment threshold to 3 BSpec: 54833 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 4 insertions(+)